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Multi-gigabit data link aggregation for next-generation systems

Gigabit serial data links have become commonplace in many of today's electronic applications. These serial data links (also called serial links) allow system developers and designers to add features and enable user experiences that otherwise would not be possible. Designers can now enable systems to incorporate rich data types such as high-definition video, stereo sound, and 3-D graphics within their application and still deliver a quality user experience.

Further, systems that do not use high-bandwidth serial links and implement their systems using slower, parallel data signaling tend to have systems with user experiences that have system lag, which results in the user having to wait for the system to respond.

The advent of multi-core processors and digital signal processors (DSPs) along with high-performance field programmable gate arrays (FPGAs) has further fueled the need to incorporate serial links within many high-performance electronic systems. These new silicon technologies are capable of handling much more data than previous generations of single-core systems.

Availability of much greater processing power has allowed designers freedom to add functionality and features that ultimately requires systems to manage more data. Many system designers are now using serializer/deserializer (SerDes) devices within their applications to enable greater data throughput for their application.

Often, designers use SerDes devices to move large amounts of data between the system’s data collection units and the data processing units. Many of today's data collection units comprise very high-performance data converters capable of generating large amounts of digital data that need to be transported to central processing units or sub-systems for analysis.

Using SerDes devices within these types of high-performance applications enable system designers to achieve the needed data transmission throughput, as well as allow for lower power consumption, reduced system size, lower system complexity, and overall lower cost of implementation.

In recent years, serial links have become more prevalent in applications outside of telecommunication and data communications. Applications such as medical imaging, machine vision, and keyboard video monitor (KVM) data distribution all have benefited from using SerDes-based system designs. Many of today's high-end DSPs, FPGAs, data converters, and microprocessors incorporate serial link interfaces. It is very common to find systems that have multiple processing units, each with their own serial link interfaces.

System designers now face a new challenge of being able to design and manage systems that have multiple serial links. In order to continue to enjoy the benefits of serial link-based data transfer, system designers need a way to consolidate these multiple serial links into a single or a smaller number of higher data rate data streams.

New SerDes solutions, such as Texas instrument’s TLK10002 as well as many high-end FPGAs, enable system designers to aggregate multiple channels of gigabit serial data into a single higher data rate data stream. These aggregated data streams then can be sent over various types of transmission media such as copper cable, copper backplanes, and optical links (when used with optical modules such as SFP+). The concept of aggregation is relatively simple in terms of its functionality, but rather complex in terms of its implementation.

The function of aggregation is simply combining multiple, serialized time synchronous data streams into a higher data-rate serial stream by interleaving the individual sub-rate data streams in a specific way. The implementation complexity arises in the process of the interleaving that occurs between the multiple individual serialized data streams so they can be de-interleaved on the receiving side of the link.

In order to accomplish this process, appropriate serial stream encoding and decoding, as well as lane demarcation and alignment, have to be implemented both on the data origination side as well as in the aggregating SerDes itself . The generalized conceptual view of aggregation is shown in Figure 1 .

 

Figure 1: Data aggregation concept

(click here to see enlarged image).

In the example shown in Figure 2 , multiple high-performance data collection units interface to a programmable device such as an FPGA, which can process the data and prepare it for transmission. Many of today's FPGAs have built-in serial links (SerDes) that can be used to transmit the data serially.

However, FPGAs with built-in serial links, especially for data rates higher than 5 Gbps, are often too complex and too costly for use in every application. In these cases, using a discrete SerDes, along with a low-cost FPGA that supports serial links rates of 3 Gbps and lower, can result in the most optimal and cost-effective solution for the application.

 

Figure 2: System signal flow

(click here to see enlarged image).

 Aggregating multiple serialized data streams can greatly reduce the complexity of an application that has incorporated multiple gigabit serial data streams in its design. Without the benefit of aggregation, these designs would need to manage all of the serialized data streams in the system. Often the serial data needs to be transmitted over some distance of media.

If each individual serial line were transmitted by itself, the designer would have to dedicate media, connectors, and optical modules for each link. This results in more board space consumption in terms of signal routing and more power consumption to drive the multiple transmitters and receivers, which in turn results in higher overall implementation costs.

Serial link aggregation within a design also enables scalability. For example, a system that implements four 2.5 Gbps (full-duplex) links needs to implement eight differential signal lines (4 TX and 4 RX) (Figure 3 ). Now imagine that this application needs to double its data throughput. In order to double the data throughput, the system needs to implement sixteen 2.5 Gbps differential signal lines.

As you can see, doubling the throughput has dramatically increased the number of differential lines that need to be implemented within the application. Most of today's applications are not able to absorb the additional resource cost of adding all of these additional differential signal lines.

With link aggregation, the same implementation reduces the original eight differential lines of 2.5 Gbps links into a single pair of serial streams, which is implemented with two differential signaling lines (1 TX and 1 RX). When the need arises to double the systems throughput, the designer only needs to add two more differential signaling lines.

This large difference in the number of serial lines that needs to be accommodated by the system has a significant impact to the overall system design. System designers can enjoy tremendous power savings by implementing aggregated serial links. Additionally, system designers are able to save board space and reduce overall system complexity.

 

Figure 3: Non-aggregated serial link implementation

versus aggregated serial link implementation

(click here to see enlarged image).

Designers may consider it convenient to aggregate the serial links within the FPGA itself. However, using a discrete aggregating SerDes and a lower-cost FPGA to do the aggregation has several distinct advantages for a designer. Using a discrete SerDes aggregating device can dramatically lower the implementation cost of a design, especially for serial links 5 Gbps and higher.

FPGAs that support 5 to 10 Gbps data links are often more complex and have more functionality than is needed by many applications. Using an FPGA just for the serial links and not being able to utilize the rest of the functionality in a complex FPGA can result in wasted resources, ultimately leading to a solution that is not cost-competitive.

Furthermore, using a large FPGA to do the data aggregation requires the designer to add a layer of complexity to their application processing function further complicating the design approach. Adding the aggregation function in the FPGA also requires SerDes design expertise that may not be readily available in the design team. In many cases, using a discrete SerDes enables a design team to get their product to market faster as discrete SerDes vendors usually provide all the necessary FPGA RTL code needed to implement the interface between the low-cost FPGA and the SerDes.

Using a discrete cost-competitive aggregating SerDes devices and an optimized FPGA solution can allow system designers to fine tune serial link implementation while optimizing power, performance, time-to-market and scalability of their application. Over the next few years, data link aggregation is likely to become one of the key tools that high-performance system designers use to achieve their design goals.

Reference

  1. See TI TLK10002 data sheet for example of sub-rate-channel lane-alignment implementation at http://www.ti.com/product/tlk10002 .

About the Author

Atul Patel is new business development manager for Gigabit SerDes products within the Communication Interface Products Group at Texas Instruments. Atul has a Bachelor of Science in Computer Engineering as well as an MBA from the University of Central Florida. He can be reached at .

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