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Multi-threading analog simulator cuts run time by 80%

Monrovia, Calif. — Tanner EDA introduced their T-Spice simulator for analog and mixed-signal chip designs which has been developed for use on computers with multiple processor cores. On average, the tool delivers 40% faster simulations on single-processor, dual-core computers and 80% faster run times on two-processor, dual-core machines. The simulator is integrated with schematic capture and waveform viewing, boosting design productivity and shortening the design cycle.

T-Spice automatically breaks down the workload into small tasks and distributes these tasks to multiple threads for processing. It parallelizes the model evaluations during the Newton-Raphson iterations using Intel's Thread Building Blocks (TBB) technology. T-Spice also uses a direct Level-3 BLAS sparse linear solver from Intel for the linear system solution.

The product generates simulations of analog and mixed-signal IC designs. It can read HSPICE and P-Spice netlist formats directly and includes a simulation manager and device modeling features. It offers support for the latest industry models, including Penn State Philips Model (PSP), BSIM3.3, BSIM4.5, BSIM SOI, EKV, MOS11, MOS20, VBIC and MEXTRAM. Proprietary numerical techniques achieve convergence for circuits, which are often impossible to simulate with other SPICE programs and device modeling algorithms allow designers to switch from the fastest table-based model evaluation to the most accurate direct model evaluation. Custom models can be created within T-Spice using algebraic expressions for voltage and current controlled sources, data from external tables or the C programming language.

Availability: June 2007
Pricing: $6,495.00 USD
Data Sheet: T-Spice simulator

Tanner EDA, 626-471-9700, www.tanner.com/EDA

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