Analog Angle Article

Multichip partitioning illustrates true engineering challenge

(An edited version of this column appeared in EE Times, October 9, 2006.)

(A related technical article appears on the Planet Analog website, click here)

I bristle at our industry's frequent promotion of technology road maps. They make the entire engineering-design process seem so mundane and routine: we'll do this, then that, then this, and poof, we'll be there, no problem. The road map completely obscures the inevitable, unexpected turns of reality, the problems, the tradeoffs, the complexities of pushing the envelope. It presumes a linear path forward and it assumes no disruptive developments, such as the transistor, integrated circuit, or LED. It makes both engineering development and scientific progress seemed like glorified administrative tasks.

Two recent events reiterated engineering's true complexity. In talking with David Robertson, Product Line Director for high-speed converters at Analog Devices, he noted that deciding how to partition the mixed-signal functions (in this case for a communications application), between two or three distinct dice is one of the most difficult up-front design challenges. The simplistic approach would be to put all the digital functions on one chip, and all the analog ones on another, so the design can use suitable processes while minimizing unwanted, mixed-signal interactions.

But this simple idea may not be the best. Why not? First, it may make more sense to put a few analog functions on the digital chip (or vice versa) to keep some feedback or control loops physically close, and also simplify or slow down some interchip interfaces. Second, there are issues of die size, modeling, testability, and available processes characteristics. For example, a high-speed, small-geometry CMOS process may also support implementation of some high-end analog functions on-chip, with the benefits of lower overall cost than the analog process.

Regardless of which path is chosen from among the numerous partitioning options, they all suffer from the same drawback of risks and unknowns. Market size, modeling accuracy, packaging options, device yield, first-silicon performance, and many other factors are simply unknown or have large uncertainty.

The partitioning dilemma is not limited solely to mixed-signal ICs, either. Steven Brightman, marketing director of Quickfilter Technologies (a vendor of single-function digital-filter ICs), says some of their customers also debate this challenge. Should they use a more-powerful DSP and have it implement the filtering functions, or instead go with a lower-cost, admittedly less-capable DSP/microprocessor, while offloading the filtering to a separate, dedicated IC? The issue again is whether to use two lesser ICs versus one bigger one. The tradeoffs are cost, real estate, power, uncertainty, risk, and flexibility.

This is classic engineering. There is no right answer, no optimal design, and no instructor with correct answer key at the end of the project. In fact, the concept of “optimal solution” is meaningless without stating that it is optimum with respect to a specific parameter, such as cost or performance. In reality, any solution will be suboptimum with respect to all of these factors, and instead will have a balance among all of them.

This sort of tradeoff analysis, along with constant uncertainty, is what engineering design is about, and it is what our road-map fixation minimizes and even denies. To pretend that we can see the future unambiguously is a disservice to engineers and the true engineering process.

0 comments on “Multichip partitioning illustrates true engineering challenge

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.