Norwood, Mass—Critical to any network node is the generation, maintenance, and performance of the system clock. The AD9549 dual-input clock generator/synchronizer from Analog Devices, targeted but not limited to SONET/SDH optical networks, implements a unique DDS (direct digital synthesis) architecture to provide greatly improved continuous and switchover performance, see Figure below.
The IC's holdover characteristic, used when an input reference clock (or clocks) fail and the IC must carry on despite lack of reference clock, is not time limited, it will continue to provide accurate clock until the failure is removed. Stability in this holdover mode is two orders of magnitude improved compared to existing solutions: approximately 0.37 ppm versus 30 ppm. In addition, the dual reference inputs of the AD9549 mean that it works and maitians clock frequency and phase, even as the system itself switches to a backup master clock when the primary one fails. User-settable bandwidth of the digital loop filter in the AD9549, down to 1 Hz, lets the designer establish the desired input A to input B switching time and performance.
(Click on image to enlarge.)
The vendor claims that the jitter specification of 600 femtoseconds is 25% better than competing devices. Maximum output frequency is 750 MHz, via a low-jitter clock doubler for frequencies above 400 MHz. Representative phase noise with a 122.3 MHz clock and 100-Hz loop bandwidth is -142 dBc/Hz at 1 kHz offset.
The AD9549, housed in a 64-lead LFCSP package, and is specified to operate over the standard industrial temperature range, is priced at $10.95 in 10k orders.—Bill Schweber
Analog Devices, Inc. , www.analog.com