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No Need to Fear: SEPIC Outperforms the Flyback

Which topology do you chose when your specification calls for a non-isolated power supply and the output voltage falls between the minimum and maximum input voltage? Is the tried-and-true flyback used, or do you take a chance with the SEPIC (single-ended primary-inductance converter) topology? The popular choice is typically the flyback due to “fear of the unknown” with the SEPIC.

However, this choice may not be the best decision. This paper explores the trade-offs between the two topologies based on both analytic and hardware comparisons and demonstrates that the SEPIC is often the best choice.

For the comparison, an automotive stereo system was selected. Table 1 presents the power supply electrical specifications. The input-voltage range is quite large, spanning 10 to 40 volts; 10 volts is provided during heavy current draw and cold conditions, while a 40-volt surge can occur when a car’s battery is disconnected. The 15-volt output voltage is in the “middle” of the input voltage range, requiring a topology that can both buck and boost the input voltage. At an output power of 26 watts, the power supply needs a reasonable efficiency to mitigate thermal issues.



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Table 1: Typical Automotive Stereo System Electrical Specifications

The specifications in Table 1 are used as the starting points to design and prototype the two candidate topologies. Figure 1 features the finished hardware. The SEPIC is on the left side and the flyback is on the right. The two designs look quite similar, because the SEPIC’s coupled inductor is the same size as the flyback’s transformer. A large inductance value (along with its physical size) is needed to keep the SEPIC converter operating in continuous current mode (CCM) at light loads.

Figure 1: Demo Board (SEPIC on left side; Flyback on right.)

Figure 2 presents a simplified power-stage schematic for both topologies. In this comparison, the flyback is also designed to run in CCM.



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Figure 2: Simplified SEPIC and Flyback Power Supplies

The power switch, Q3 , is turned ON to store an incremental amount of energy in the transformer. It is then turned OFF and the transformer’s secondary voltage reverses. Current is forced through D6 into the output where energy from the transformer charges the output capacitor and is delivered to the load. Regulation is achieved by controlling the duty-factor and the incremental energy into the system. Both the power switch and diode have unclamped inductive switching; that is, the voltage placed on them is controlled, to a large degree, by the transformer leakage inductance and stray capacitance. This unclamped leakage causes ringing amplitudes that can easily be 50 percent greater than the calculated voltage stresses, and require higher voltage devices to be selected.

The schematic on the left of Figure 2 shows the SEPIC-converter power stage. When Q6 is ON, the C26 positive terminal is held at ground. At the same time, T2 ’s 1:1 turns ratio places a voltage equal to negative Vin on C26 ’s negative terminal. This means that the capacitor has the input voltage applied across it with the polarity shown. While the switch is ON, an incremental amount of energy is stored in the primary inductance. Current flows in the inductor secondary and coupling capacitor (C26) to equalize its charge.

When the switch is turned OFF, the voltages on both windings of T2 reverse. When D9 conducts, both windings are clamped to the output-voltage levels. The drain voltage of Q6 rises to Vin plus Vout. During Q6 ’s OFF time, current flow from both primary (through C26 ) and secondary (through D9 ) is provided to the output.

This circuit has the advantage that both the FET and diode voltages are clamped by the capacitors, so there is little circuit ringing. It might seem that the SEPIC “pays a penalty” since the C26 coupling capacitor has significant ripple current. However, this penalty is offset somewhat by the fact that the SEPIC’s continuous input current significantly reduces the ripple current in the input capacitor (C19 ). The SEPIC topology has another advantage, with power being simultaneously drawn from the input and delivered to the output, much like that of an auto-transformer. Because the power switches do not have to handle the entire power transfer, the circuit is more efficient.

Both converters were designed to operate at identical maximum duty-cycles, which occur at the minimum input voltage. This provides a fair comparison between the two topologies, based only on the circuit’s performance merits at identical operating conditions. Table 2 compares the circuit stresses of the two topologies, both analytically and numerically. This table assumes a very small inductor ripple-current (infinite inductance) and ideal diodes, to simplify the equations.



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Table 2: Flyback and SEPIC Converter Design Equations
(L is Assumed to be Infinite; Diodes are Ideal)

Note that both converters have the same 1:1 transformer turns ratio, since they both operate at identical duty-cycles. Capacitor ripple currents are identical for both topologies, when the flyback’s input capacitor is compared to the SEPIC’s coupling capacitor. These capacitors should have similar voltage ratings because they are each charged to the input voltage. Both topologies have large ac-ripple currents and must use low Equivalent Series Resistance (ESR) capacitors. Both converters have the same output capacitance requirement, since each must fully support the output load current during the diode’s OFF time.

Table 2 also shows that the SEPIC and flyback have identical FET and diode voltage stresses. However, the flyback must switch an unclamped inductance and has a significantly higher FET voltage stress and diode Peak Inverse Voltage (PIV) than the SEPIC. Because the flyback requires a higher-voltage-rated FET, the conduction losses increase by approximately 50 percent due to the FET’s higher Rds(on). The large voltage spike will also increase the switching turn OFF losses relative to that of the SEPIC.

The negative voltage spike on the flyback transformers secondary makes a Schottky diode unacceptable and forces the use of an ultra-fast diode, with its higher conduction losses and correspondingly lower efficiencies. Voltage spikes on the power switch and output diode caused by the flyback transformer leakage inductance usually require a voltage clamp and/or snubber circuit to limit the peak voltage, further reducing efficiency. The flyback’s only significant component advantage is that its smaller inductance requirement. The inductor’s volume is generally related to the energy storage requirement of L times I, with the flyback requiring about one-half the SEPIC’s energy storage. This lower energy-storage requirement typically allows the flyback’s inductor to be smaller than the SEPIC’s inductor.

However in this example design, the discrete core sizes available did not allow use of the next smaller core. If a smaller core is of particular importance to a designer, the critical inductance can be lowered by designing for a smaller maximum duty-cycle, operating at a higher switching frequency, or by raising the minimum output power to stay in continuous mode operation.

Figures 3 and 4 show the prototype hardware circuit schematics pictured in Figure 1. Each circuit occupies approximately 4.5 square inches of component area and uses an identical number of power components. The flyback circuit uses several additional components over the SEPIC that are mostly accounted for in the snubbers. Both designs use the UCC3807 controller, which allows an adjustable duty-cycle limit greater than 50 percent. In this application, it is set to a 75 percent maximum.

The flyback uses two input capacitors rated to handle the large AC rms requirement of the pulsating current generated by the FET switch. When compared to ceramics, the large-value, low-cost aluminum electrolytic capacitors work best because their large capacitance can provide a low input-ripple voltage. The SEPIC’s significantly lower rms input ripple current “relaxes” the input-capacitance requirement. With the SEPIC, only one input capacitor is required to handle the triangular inductor current’s rather low AC rms rating. However, two higher-rms-current rated ac coupling capacitors are required on the SEPIC. These components have the same stress equations as the flyback’s input capacitors.



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Figure 3: Flyback Converter Design



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Figure 4: SEPIC Converter Design

In Figure 5 , the waveforms show the FET drain voltage present on the flyback and SEPIC circuits. The waveforms were taken at maximum output load and a 12 Vdc input. The flyback-transformer leakage inductance produces a voltage spike that adds an additional 15V to the “flat-top” voltage. In comparison, the SEPIC FET switching waveform is clamped and shows very little overshoot, or ringing. This clamping results in lower switching losses and noise, as well as a power stage that can be operated at a much higher frequency than that of the flyback.



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Figure 5: Power FET Drain Waveforms (10V/div)
(Flyback on top; SEPIC on bottom.)

Figure 6 shows the flyback and SEPIC output-diode switching waveforms. Again, the flyback transformer leakage inductance produces a significant voltage spike relative to the SEPIC. A 200V output diode is required for the flyback to handle the large negative ringing, compared to the SEPIC’s 60V Schottky diode. The 0.5-volt forward drop of the SEPIC’s Schottky diode relative to the 1-volt forward drop of the flyback’s ultra-fast diode results in significant power savings for the SEPIC.



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Figure 6: Output Diode Waveforms (20V/div)
(Flyback on top; SEPIC on bottom.)

Figure 7 shows the efficiency of both circuits measured at two input voltages. The SEPIC generally achieves two-to-three percent higher efficiency overall than the flyback, reaching a peak efficiency of 92.7 percent. Component dissipations are similar for both circuits excluding the FET, output diode and snubbers.



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Figure 7: SEPIC Provides Better Efficiency than the Flyback Converter

While the relative simplicity and familiarity of the flyback converter has its advantages, the SEPIC converter can provide higher efficiency and lower component stress. Table 3 compares the two approaches. The SEPIC is more efficient because semiconductors with lower voltage ratings can be used, due to lower circuit-voltage stresses. Component count is similar for the two designs, but the flyback has the disadvantage of requiring snubbers.

While the component areas are equal, the flyback’s transformer could be made smaller because its inductance requirement is one-half that of the SEPIC’s. Continuous input current not only reduces the SEPIC’s input-capacitor ripple-current rating, but it also improves a system’s electromagnetic emissions. If there are other loads on the 12-volt input, the flyback’s discontinuous input current is more likely to generate an unacceptable ripple on the input, which may require additional filtering.

One downside of the SEPIC is that it has an additional passive component, an AC-coupling capacitor, which complicates the control characteristics. However, when implemented correctly, the SEPIC converter provides an excellent, highly-efficient solution.



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Table 3: SEPIC can offer significant advantages over Flyback

About the Authors
Robert Kollman and John Betten are at Texas Instruments, Inc, www.ti.com. Mr. Kollman is a Distinguished Member, Technical Staff, and is a Power Management Applications Manager there. He is a nationally-recognized power supply expert with more than 30 years of power-electronics experience and has authored more than 40 papers in the field. Mr. Kollman has a BSEE from Texas A&M University and a MSEE from Southern Methodist University. He can be contacted at r-kollman@ti.com.

John Betten is an Application Engineer and Senior Member of the Technical Staff at Texas Instruments. John has 20 years design experience in the field of AC/DC and DC/DC power conversion. He has published more than 20 articles and has been awarded one patent. He received his B.S. degree in Electrical Engineering from the University of Pittsburgh, PA. John is a member of IEEE and can be reached at j-betten@ti.com

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