Analog Angle Blog

No place to hide from PCB thermal and RF considerations

A very long time ago, in the “old days” of lower frequencies and discrete point-to-point wiring, what was mostly needed to build a physical circuit was schematic, a fulfilled BOM, and perhaps an associated assembly drawing done before construction. That was it. The basic schematic diagram showed the interconnection between the circuit components and often had some useful notes such as “do not place component x near component y”. The constructed circuit had issues of wire routing and cable harness, and those were tangible and immediate.

Those days are long gone and PCBs now rule our world. These PCBs range from inexpensive, single-sided, punched phenolic boards of low-end consumer products to boards with multiple layers, thin traces, tight-trace spacing, and countless vias between layers. Here, it’s worth mentioning that via stands for vertical interconnect access, but it’s rarely spelled out these days.

Without these dense boards and their capabilities, we’d be stuck; it’s that simple. Smaller components lead to tighter boards and tighter boards support ever-smaller components. It’s now common to have passive and active components with dimensions on the order of a few millimeters on a side or even less.

PCB thermal issues

These high-density PCBs have significant thermal and RF issues. Fortunately, there’s help available. I recently saw a copy of a new book with the no-nonsense, direct title “PCB Design Guide to Via and Trace Currents and Temperatures” by Douglas Brooks and Johannes Adam (Artech House, ISBN 978-1-63081-860-9). This hefty 246-page book tells you everything you need or want to know about thermal issues related to PCB traces and layouts (Figure 1).

Figure 1 The book gets right to the point with its title: it’s all about PCB traces and vias. Source: Artech House

The book, which goes far beyond the basics, can unintentionally induce fear in a board designer’s heart and mind. If your knowledge of thermal issues associated with PCB traces begins and ends with the important industry guideline “IPC-2152: Standard for Determining Current Carrying Capacity in Printed Board Design,” you need to be a lot more aware, as that standard is only the tip of the iceberg.

Among the many issues the book covers include sensitivity analyses, showing what happens when operating environments vary. That encompasses effects on adjacent traces and planes, changing trace lengths, and presence of thermal gradients, along with fusing issues and consequences of overloading traces. It also looks at the well-known impact of voltage drops across traces and vias, the thermal effects going around right-angle corners, and how frequency effects are covered.

The PCB trace “fusing” issue resonates personally. Many years ago, while working on a project, we had board traces for DC rails carrying 10 A, and they were conservatively sized for that current except in one small place. The board designer/layout person manually “necked down” the trace to a thin hair of a few millimeters, so it could “sneak around” a larger component. After a few months, we were having random field failures on the DC rail distribution tree.

Long story short: that tiny sliver of a trace was acting as a fuse due to I2R dissipation at the spot and opening at random times, depending on the current level and duration, operating environment, and other factors. It took a while to narrow down and trace the problem (puns intended). Fortunately, the rework fix was easy: a small jumper wire was soldered onto the board in parallel with the thinned trace, solving the problem entirely.

RF issues on PCBs

Of course, a PCB is much more than traces and planes carrying DC; there is also an RF world with clocks and frequencies spanning into the hundreds of megahertz and gigahertz. Ironically, the RF and DC worlds do overlap as parasitics of various types and current-flow paths directly impact RF performance and complicate models, and faithful models of this situation are challenging.

Coincident with this book, I came across a PowerPoint presentation with a modest, almost innocent title “The ‘Ground’ Myth” by Dr. Bruce Archambeault, an IBM Distinguished Engineer and IEEE Fellow. Although it may seem ancient due to its 2007 date, the lessons of this very readable, clear, and nicely illustrated presentation are timeless and especially relevant today. Despite its length of 105 slides, it never feels overwhelming as it’s simple yet not simplistic. There are many similar presentations available online in various guises and lengths, and it’s one of the best of the many I have read.

Each of the five main sections—electromagnetics, skin effect, inductance, ground, and return current path—has just enough background and theory for the needed context and has practical explanation and crisp, informative, and clever illustrations. There is even some good-natured humor, which is not easy for this topic. Some of the points are obvious but worth repeating, others are less obvious (Figure 2).

Figure 2 The simple drawing of current flow is a clear reminder of basic rules overlooked due to the pressures of design and development process. (Image source: Bruce Archambeault)

What I find especially interesting about these two resources is that they do not involve complicated analysis, deep physics, or intense math. Both the book and the PowerPoint presentation embody a “back to basics” perspective with an expanded restatement and reminder of fundamentals, yielding an updated perspective of what designers need to be aware of as design “on paper” becomes tangible.

It’s easy to get wrapped up in high-level field and differential equations, but for solid engineering, basics matter for IR voltage drop, I2R dissipation, thermal fundamentals, impedance, and current paths that make the difference between a good and reliable design versus one which is marginal or worse. After all, a perfect schematic and bug-free software—or at least bug-light software—are necessary but not sufficient for a well-executed product.

Have you ever found basics such as PCB trace sizing and thermal issues, or DC and RF return currents, to be the biggest “headache” in qualifying a design? Did you appreciate the challenge early on, but struggled to convince others of the potential for problems?

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