Not All Design Limits Should Be Equal Especially For MOS Transistor Design

If you have designed blocks in submicron technologies you realize that supply voltages make circuit designs difficult. In the newer technologies, the supply voltage continues to shrink. So how does an analog designer design on technologies where the maximum core voltage is dropping to the one voltage region of operation. The immediate response may be to use higher voltage transistors as a higher 5V or 3V transistor is usually available. However, using the higher voltage transistor has its own draw backs. Many of the limitations from using higher voltage transistors become more apparent if the analog block being designed is high performance or requires speed. In addition, once a block is designed using the higher voltage devices the outputs of these blocks must interface with other blocks that may not be designed at the higher supply voltage. This can become very problematic. So what to do? Many designers opt to use the lower voltage devices that have the speed that is needed but will need to accommodate for the smaller voltage supply.

What does this mean? Because of the smaller supply voltages designers are forced to operate the transistors at the edge of linear mode of operation. As you may know, if the transistor enters into this linear mode the gain, output impedance, Ft, and other parameters change. Most of the time this is not the desired result. Therefore, designers must understand where it is acceptable to bias their transistors to avoid moving into the forbidden realm. This is the topic I would like to discuss.

Some of the important parameters to monitor when setting biasing conditions for transistors are the following:

  • Gm /ID
  • Vgs -Vt
  • Vds -Vdsat
  • Ft

This list is not exhaustive by no means but does highlight some of the most important analog metrics to watch for when designing analog blocks. These metrics and the allowable range will be different depending on the technology used and must be optimized per the technology and device type (whether the device is a PMOS or NMOS transistor). To do this, I suggest you ask the technology team where you work if the models are first of all acceptable for accurately simulating the above metrics. Second, I would setup test benches to look at the metrics outline above and set the limits for these based on the technology and what your design lead says is an acceptable region of operation.

I want to make one point, there will be exceptions to the very criteria you outline. For instance, over corners you may find a violation in the very parameter set conditions established by the design team. In these cases, please check to see if the simulation condition is a valid use case. It seems appropriate to not want to redesign transistors for a specific bias condition if the performance of your blocks function does not significantly degrade under such conditions. Judgments must be made. So, what is a starting point for of the metrics outlined? May I suggest the following?

  • Gm /ID <20
  • Vgs -Vt
  • >100mV

  • Vds -Vdsat >100mV

Here you must be cautious to not overdesign a transistor. For instance, the PMOS |Vds -Vdsat | can be much smaller in magnitude than an NMOS transistor in a similar condition. The way to tell is to look at the output impedance or GM /ID and see if there is any significant change. If not, then maybe |Vds -Vdsat | can be reduced (say ∼50mV) without having issue under your casing design. This is the type of explorations I suggest are carried out at the beginning phase of a project. This is especially true if the designer has not completed designs on the specific technology node targeted and is unfamiliar of the process limitations.

Do you agree with the conditions outlined?

Do you have other criteria that you believe is more appropriate?

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