Have you ever designed a part and have been eagerly anticipating the first silicon out to see if your designs work as anticipated? In preparation for this event, you design an evaluation board to measure the part you developed. Have you ever found out that the board designed works OK but does not meet the expectations for the design? If you are designing basic low frequency designs then a generic design of an evaluation board may be ok, but not always. What about evaluating high frequency circuits or circuits with high dynamic range and low noise? I would like to discuss this topic.
Designing an evaluation board requires that the designer develops the circuit with the design of the evaluation board ever present during the design process. The design of the evaluation board cannot be an afterthought. The evaluation board must be thought of during the silicon circuit design with thought placed on how to extract reliable data from the circuit and how to place test signals and or biases into the part. The design of the analog evaluation board (from now on noted as AVB) is particularly important when the outputs of the circuit are digital in nature and the inputs are sensitive small signal analog signals. In addition, this criteria applies when the signals collected are from low noise floor LNA’s etc. As part of this exploration, I will discuss some of the issues when testing a high speed wide dynamic range ADC.
When designing the AVB for evaluating the ADC, it is important to design the output drivers to properly interface with the AVB for the lowest noise and most isolation. Depending on the number of digital type outputs and the rates at which the outputs change, including the edge rates of data changing, the interference from these signals can create isolation problems. To address this concern, often times it is appropriate to develop specific output drivers that can take out the signal at low levels.
Shown in figure 1 is an example of such a driver that is designed on the part and not the board. Unlike a true LVDS driver that requires additional pads and circuitry, the driver in figure 1 is a simple output current with control of the swing dictated by an external resistor on the AVB. Note, the signal “v_driver” in the figure should be derived from a dedicated LDO with significant decoupling using various caps sizes (see blog “Capacitors: Bigger Is Not Always Better”). Also note “r_ext” on the figure represents an on board resistor that is set based on the swing desired and can also be used to set the rise times of the signals output.
For this ADC example, these digital type outputs using the proposed driver circuit enable the swings of the outputs to be set around the trip point of the logic analyzer collecting the digital data. By setting the levels around the desired trip point, the output signals are collected in a way to avoid problems with isolation on the board. One last point to discuss on developing the driver circuit as shown in figure 2. It is important to ensure each driver has its own dedicated ground to avoid interaction through a shared impedance.
Because the circuit is basically a digital voltage to current generator, the modification of the VGS of each driver’s transistors can be modulated by other outputs that share a same ground wire route inside the package. Therefore, do not share the grounds between the drivers as shown in figure 2. However, the driver is not the only issue to consider. What about bringing clock signals onto the part?
To bring on clock signals into the part without killing isolation or causing unwanted interference, a special buffer like the one in figure 3 can be designed on the part. The idea is to input a small signal sine wave with low edge rates and gain up the signal inside the part to create CMOS levels needed to drive your circuits. This design could be as simple as an inverter in feedback or something more complicated to generate the gain, but the idea is the same. Gain up the signal until a comparator type circuit is used to create the desired CMOS levels inside the part. By using low edge rate input signals into the part, the kickback and unwanted ringing from large edge rates are avoided resulting in improved isolation as well.
These principles are not complete without a study of the routing, power, and grounding on the AVB. When designing the AVB, the routing and grounding is paramount to a successful AVB. It is important to look at how currents on the board will travel and treat the board as an extension of the circuit layout of the part. This means that currents from the part into the ground must return to the source that generated the current. With that being said, some may think of creating separate digital ground planes and analog ground planes. This does not work so well for high frequency circuits or circuits that have large edge rates.
Where does the current flow? So, watch for circulating currents from your part. There are times when providing a separate ground plane can work well as long as the circulating currents can be kept locally to the ground plane and do not need to return to your circuit ground through some unknown parasitic. So the best solution is to use flooded ground planes that are all connected together. What about the power planes?
For the power routing, the power distribution can be in the form of a power plane or can be treated as wide routes if the current is not large enough to create undesired IR drops. Furthermore, the case for power routes can improve isolation by reducing coupling capacitance from different sources of digital power and analog power. Lastly, it is important to treat differential inputs as differential all the way from the test port to the DUT pin. Once the board has been routed properly, do not forget about the package and socket as these are just as critical to a successful AVB.
As stated, we must not forget about the package and socket used for the evaluation on the AVB. Regarding the package, one of the best packages for evaluating circuits that I have found are standard type packages such as a QFN with an exposed flag. Shown in figure 4 are pictures of example implementation of using a QFN package. As shown in figure 4, the exposed flag is the key as it provides the ability to down bond all of the grounds to a low inductance connection to the board ground. In addition, the down bonds are shorter in length compared to the bond wires needed to attach to the lead frame further reducing the inductance of the grounding impedance.
Lastly, we cannot forget about the size of the board. Understand the limits and criteria for the signals being measured. Are the signals sensitive to external influences? If this is the case does the board need to be small enough to fit into a shielded cage? What about isolation between ports. Is the board large enough to avoid various data collecting ports and or function on the board from interacting? Sometimes it may be necessary for the board to be design to test a specific function of the part and a separate board for testing the remaining functions.