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NRE Costs & Analog Integration

We've talked about analog integration from several different perspectives — what parts we'd like, why we'd like them instead of a number of individual ICs, what it might take to get IC manufacturers to do what we want… Now, it's time to look at why those manufacturers are not lining up to meet our needs: cost.

We had a chat session last week. Some points regarding analog fabrication came up. From the discussion, I gathered some information and had an interesting conversation with a couple of our regular bloggers, Scott Elder and Blaine Bateman. First up, Scott.

Scott gave me some ballpark numbers on the non-recurring engineering (NRE) costs associated with a new device. At 28 nm, the design cost is $50 million to $90 million. Each mask set is $2 million to $3 million. If you're lucky, you'll get away with going through the mask creation process twice to get the design done. Not lucky? Then more iteration.

Going down to 22/20 nm, the design cost is $120 million to $500 million, and a mask set costs $5 million to $8 million per iteration. Finer lines, higher cost.

Scott rightly notes that not many products can support that much NRE. Only ICs that end up in products that everyone buys can support this level of cost — for example, products like cellphones. Scott said, “How many $1 chips do you need to sell to recoup $100 million? And then at these really high volumes, the margins are low. Very hard to make money.”

At 180 nm, mask cost are around $150,000, and design cost is around $1 million to $2 million. So more companies pursue 180 nm — or maybe down to 130 nm. We may see some of the companies that are mostly doing analog push down to 90 nm, but probably not much farther.

The analog companies generally lag behind the digital companies by three generations. The digital guys are at 28 nm. The analog guys are at maybe 130 nm (with 45 and 65 nm in between).

Do you really need to go below 90 nm for your analog parts? If you do, you'll need a large team to do the work. If you're doing digital, you can grab IP from multiple companies, but doing that with analog probably won't work. Anyone doing analog wants to do the IP themselves so that they are sure they get just what they want for each piece. The digital guys don't care much about the individual pieces — just the big picture. So they will snag a PLL here, a SerDes there, an ADC or DAC somewhere else…

What can we take from this? Do we give up? Nope. From Blaine Bateman:

I have heard about situations where older fabs tooled for either smaller wafers or lower resolution nodes have been used to bring up MEMS processes (I think) and I was speculating as to whether some of the analog integration could do the same thing. At the current bleeding edge of tens of nanometers for processor ICs, only a few companies (like Intel) can afford to even tool the next node. But I'm not sure that other advances in integration need the density of the latest Pentium chips, etc.

I think someone commented that in some portions of the market, analog integration has to follow the digital along the new process nodes. But I was wondering if pure analog or “lower speed” mixed signal (i.e., not GHz level CPU + analog) chips might be built on older process nodes. This is speculation on my part but if true, the entire capitalization cost equation changes dramatically.

So the key to keeping the cost under control is to not make yourself crazy pursuing the bleeding-edge technology for IC fab. It is likely overkill. Instead, work with suppliers who specialize in working at or around 180 nm. They likely have slots available to do your work and will be more affordable.

How much analog design do you see happening below 130 nm? Or below 90 nm? What's been your experience down at these tiny geometries?

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10 comments on “NRE Costs & Analog Integration

  1. RedDerek
    August 29, 2013

    When I was looking for funding for a start-up fabless company, we were focusing on larger features, 0.5u or larger. This brought development costs down significantly. With many companies going down in feature size to cut cost of production is fine. But, as you say, the mask set cost go up and the volume has to go up to a product that everyone would buy.

    This leaves the small market segment of specialized products out. It also forces the operation voltage to go down as well. There is still a market for higher voltage processes out there.

    BTW, the fabless company I was looking to start was focusing on 30V and higher process with some very unique approaches to circuit applications. I had one that was able to cut the off-line power consumption below what is being thought of “low” today; and this was 8 years ago. Oh well.

  2. Scott Elder
    August 29, 2013

    “…and this was 8 years ago. Oh well.”

    Eight years is not a long time in analog….

  3. Steve Taranovich
    August 31, 2013

    What about larger wafer sizes? The larger wafers can yield more than twice as many chips or more, achieving an economy of scale that will save money in manufacturing costs for each wafer.

    Granted that as the wafer size increases, so does the difficulty of getting perfect chips from that wafer every time, and so does the ability of equipment makers to design tools to handle the wafers. Since companies like Intel usually lead the market in these types of efforts, then the equipment makers will follow their lead and then analog companies will benefit.

  4. SunitaT
    August 31, 2013

    Anyone doing analog wants to do the IP themselves so that they are sure they get just what they want for each piece.

    @Brad, thanks for sharing the cost numbers. I agree with your opinion that many companies wants to IP themselves because they want to meet the exact spec and this is what makes analog design more challenging.

  5. SunitaT
    August 31, 2013

    The larger wafers can yield more than twice as many chips or more

    @Steve, isnt it true that larfer wafers means more varation on chip and thus we will have lot of mismatch issues ? Isn't it better to opt for smaller wafers in analog so that we can reduce mismatch related issues.

  6. SunitaT
    August 31, 2013

    There is still a market for higher voltage processes out there.

    @RedDerek, I totally agree with you. I think most of the industrial applications require highvoltage decvices and thus this demand will always exist.

  7. David Maciel Silva
    August 31, 2013

    Despite a strong change in both the manufacturing processes of integrated circuits, such as the changing needs of the industry, I believe that some items and how to manufacture them will not change.

    For those who do not yet know much about the design of integrated circuits, one interesting video:

    http://www.youtube.com/watch?v=l7-EmE7Ixuo

     

  8. Steve Taranovich
    August 31, 2013

    Hi SunitaT—Mismatch really depends upon many variables such as supply voltage, line width of the process and wafer size. It's far more complex than is evident, so you can't generalize. There are some very good IEEE papers that go into detail on this.

    Every change has a compromise, so it depends upon what features you are willing to compromise

  9. samicksha
    September 2, 2013

    @Sunita: You kept a good point here but in some case we can use devices with matched geometrical shapes so they have matched variations or you can make device large so that variations can be ignored.

  10. Brad_Albing
    September 3, 2013

    @RedDerek – that part you mentioned in the last paragraph – sounds interesting. Might be a blog in there….

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