NXP's JEDEC-based data converters include two analog-to-digital converters (ADCs)the 12-bit ADC1213Dxx and 14-bit ADD1413Dxx and a digital-to-analog converter (DAC), the DAC1408D650.
The ADCs operate at sampling speeds of 65, 80, 105, and 125 MSPS, Other ADC specs include SNR: 73 dB typical, SFDR: 90 dBc typical. For the DAC, the output rate is 650 MSPS, and it includes a 32-bit numerically controlled oscillator (NC)) frequency synthesizer.
NXP's JEDEC-based data converters are fully interoperable with cost-effective FPGAs from Lattice, Altera and Xilinx. They are targeted at cellular base stations, medical imaging equipment, high-speed instrumentation, video broadcast equipment, and military data acquisition applications.
The JEDEC JESD204A interface typically uses six interconnect signals for a 14-bit dual-channel data converter, nearly an 80% reduction compared to a parallel interface that typically consumes 28 interconnect signals. The JEDEC JESD204A interface also provides higher interconnect signal integrity, single-bit error detection, and enables system performance scalability without PCB design changes.
Samples of NXP's JESD204A data converters are now available with lead customers. Commercial samples will be available to the broader market from Q3 2009.