Phoenix, Ariz. ON Semiconductor has unveiled its PureEdge family of phase lock loop (PLL) based clock generation devices that is said to deliver 50 percent better phase jitter than competitive products for consumer, networking and telecommunications applications.
The first PureEdge devices available are the NB3N3001 and NB3N3011. Suitable for FibreChannel and Serial ATA (SATA) applications, these devices are 3.3 volt (V) clock generators with LVPECL differential outputs.
The NB3N3001 uses an inexpensive reference crystal to generate a differential LVPECL output clock at 106.25 MHz or 212.5 MHz. It provides a typical root mean square (RMS) phase jitter of less than 0.3 ps and noise floor of -135 decibels relative to the carrier per hertz (dBc/Hz) at 100 kilohertz (KHz) offset from the carrier frequency.
The NB3N3011 uses an inexpensive reference crystal to generate a differential LVPECL clock signal of 100 MHz or 106.25 MHz. It provides a typical RMS phase jitter of less than 0.3 ps and noise floor of -135 dBc/Hz at 100 kHz offset from the carrier frequency.
ON Semi said the typical 0.3 ps RMS phase jitter measurements provide a 50 percent reduction compared to competitive devices over the 637 KHz to 10 MHz range. In addition, a phase noise of < -135 dBc/Hz at 100 KHz offset delivers a 5 dBc/Hz better phase noise performance than competitive devices, according to the company.
Both devices are pin compatible drop-in replacements for competitive function devices the ICS843001 and ICS843011.
ON Semiconductor , 1-602-244-6600, www.onsemi.com