Optimizing gate timing with external FET driver for high-input-voltage step-down converter

Many industrial applications require a non-isolated, low-voltage supply from a high-voltage input. To extend the input-voltage range of a regulator that could not normally accept the high input-voltage, high-voltage external MOSFET drivers can be used.

Figure 1 shows a high-input-voltage buck circuit using a LTC3731 switching regulator with a LTC4440 high-side gate driver.

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Figure 1: An external gate driver (LTC4440) at the top gate extends the input-voltage range of a LTC3731 synchronous-buck converter

The LTC3731 is a 3-phase synchronous buck regulator, which we chose for its high efficiency with high input-to-output voltage differentials. Its rated maximum input is 36V, but that limit is imposed entirely by the integrated FET drivers. We extend the input range of the regulator by bypassing the integrated FET drivers, and use the LTC4440 FET driver, which is rated for 80V.

The gate timing of the top FET and bottom FET in a synchronous buck converter is critical. As shown in Figure 2 , the external driver LTC4440 introduces a propagation delay from the LTC3731’s top driver output (TG) to the top FET gate signal Qtop .

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Figure 2: Extra rising-edge delay is needed for the bottom gate, to account for the delay induced by the external LTC4440 FET driver at the top gate

Although the LTC3731 has built-in deadtime, it may not be sufficient when considering the delay time introduced by LTC4440. Sufficient deadtime is needed to avoid a possible short-circuit from the top FET to bottom FET. Something is needed to delay the rising edge of the bottom MOSFET gate signal Qbot .

Figure 3a shows a popular RC delay circuit used to slow down the rising edge of gate signal and increase dead time. This RC circuit is often followed by an edge-shaping circuit, to improve the slow rising edge which would otherwise cause additional switching loss. Unfortunately, the edge-shaping circuit requires an extra driver circuit, often at significant incremental cost.

Figure 3a: RC delay

Figure 3 shows an alternative, LC-based passive delay circuit. Cdly could be the equivalent gate capacitance of the driving MOSFET.

Figure 3b: LC Delay

D1 and D2 are both Schottky diodes. D1 is used to speed up the falling edge and D2 is used to block the unnecessary ringing during turn off. Figure 4 compares the simulated waveforms of the rising-edge delay with RC and LC methods to achieve the same delay time target. Vsw is the switch node voltage waveform.

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Figure 4: Simulated rising-edge delay waveforms using RC and LC delay circuit

The LC delay has a sharper rising edge, thus extra shaping circuits are not needed.

Figure 5 shows the measured rising edge and switch-node waveforms of the LC and RC delay circuits.

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Figure 5: Experimental rising-edge delay waveforms using RC and LC delay circuit shows the LC delay will have less diode-conduction time

The higher gate-drive voltage of the LC method could benefit DC/DC-converter efficiency. The LC delay method could also help converter efficiency due to the reduced period for body-diode conduction.

About the Authors
George Yu and Henry Zhang are with Linear Technology

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