**Introduction**

Radar has a broad host of applications, including detecting other automobiles and tracking flying objects; it’s even used in medical applications. The general concept is to detect the location of another object by sending out a signal and measuring the time it takes for that signal to return. Since the signal speed, *c* , and return time, Δ*t* , are known, it is possible to calculate the distance, *d* , as shown in Equation 1:

There are two common architectures for radar. The first architecture, shown in Figure 1, uses a digital-to-analog converter (DAC) to tune the frequency of a voltage-controlled oscillator (VCO) in order to generate the appropriate waveform.

**Figure 1**

**Radar waveform generation using a DAC**

This approach is good for generating waveforms that can abruptly change frequency. Control of the frequency’s accuracy requires some compensation, however, because the VCO frequency can vary significantly over process, voltage and temperature.

The second architecture, shown in Figure 2, uses a phased-locked loop (PLL). This approach improves frequency accuracy, but introduces challenges associated with how fast the frequency can change.

**Figure 2**

**Radar waveform generation using a PLL**

In this article, I’ll discuss the PLL architecture and give some background on the maximum frequency change possible with this approach.

**Common modulated radar waveform types**

In a radar application, the actual shape of the waveform varies based on the needs of the specific application. In situations where the object to be detected is far away, the waveform transmitted may be a quick pulse; you can use the time it takes for the reflected pulse to return to calculate d. In situations where the object is not moving very fast, the waveform shape may involve abrupt frequency steps, as shown in Figure 3. Stepping the waveform can sometimes be easier to implement from a hardware perspective, but may require more back-end processing.

**Figure 3**

**Stepped waveform example**

A third style of waveform is the chirp/ramp waveform shown in Figure 4. This waveform starts at one frequency with a linear ramp of known slope, *m* . Based on the speed of light and the difference between the transmitted and measured change in frequency, Δ*f* , it is possible to calculate the distance to the target, as shown in Equation 2:

**Figure 4**

**Chirp waveform example**

A fourth style of waveform is the triangle waveform, as shown in Figure 5. By adding an additional downward slope, it is possible to detect the speed of the moving object as well as its position.

**Figure 5**

**Triangle waveform example**

The PLL architecture approach shown in Figure 2 can produce nice linear ramps, such as the ones shown in Figures 4 and 5. However, the loop bandwidth of the PLL, BW, will introduce limitations on the fastest possible ramp rate, m_{MAX} .

**Deriving the maximum ramp rate using the analog PLL model**

You can use the traditional analog PLL model shown in Figure 6 to determine one of the restrictions on the maximum ramp rate.

**Figure 6**

**PLL analog model**

The first step in determining the maximum possible ramp rate involves calculating the loop filter impedance, *Z(s) * , in terms of time constants *T1* and *T2* , and the loop bandwidth in radians, *ωc* , as shown in Equations 3 and 4. (Reference [1] derives these equations.)

Using more formulas from reference [1] and the simplifying assumption of a 45-degree phase margin and gamma optimization parameter of 1 yields the relationship expressed by Equations 5 and 6:

Substituting Equations 5 and 6 into Equation 4 yields the relationship for the total loop filter capacitance, *A* 0, expressed as Equation 7:

*A* 0 is the total capacitance, from which you can now calculate the slew rate (Equation 8):

Approximating this yields a simple rule of thumb (Equation 9):

**Deriving the maximum slew rate to avoid cycle slipping**

Although Equation 9 gives an indication of the maximum slew rate based on the analog PLL, the digital sampling action of the phase detector can also cause an effect known as cycle slipping that will distort the waveform. According to reference [1], a rule of thumb to avoid cycle slipping is to satisfy Equation 10:

where *fPD* is the phase detector, *f* 1 is the starting frequency and *f* 2 is the ending frequency.

However, Equation 10 is based on the amount of time it takes for the accumulated phase to change enough to cause a cycle slip, assuming that the frequency changes from *f* 1 to *f* 2 immediately. The reality is that this is a linear ramp from *f* 1 to *f* 2 , not an instantaneous change. Because phase is the integral of frequency, the phase error will accumulate at exactly at half the rate, introducing a factor of 2. Thus, Equation 11 is the proper formula to use:

After dividing both sides by Δ*t* , Equation 11 can be rearranged to Equation 12:

where *N* is the PLL feedback divider ratio.

**Putting the ramp slew-rate models to the test**

In order to confirm that Equation 9 actually models reality, I used a Texas Instruments LMX2492 PLL with an 800-kHz loop bandwidth. I measured the slope switching from 9,400 MHz to 9,000 MHz. Figure 7 shows the resulting slope measurement of 1,100 MHz/μs. I had to use the negative side of the slope because the restriction imposed by Equation 12 would take effect before the slew-rate restriction.

Based on the results shown in Table 1, there is reasonable agreement between the calculated and measured results, but not exactly the same value. Recall that Equation 9 was based on several simplifying assumptions, so I did not expect an exact match.

**Figure 7**

**Ramping waveform negative slope measurement**

**Table 1**

**Negative ramping slope: measured vs. calculated**

To put Equation 12 to the test and see the impact of cycle slipping, I used the same setup except with a positive slope; I also varied the slope by changing the final target frequency at the end of 5 μs. The results are shown in Figure 8.

**Figure 8**

**Positive ramping slope: maximum frequency change**

Somewhere between m= 140 MHz/μs and m = 160at 800 MHz/μs, cycle slipping started to occur. This agrees very nicely with the calculated value of m_{MAX} = 145 MHz/μs in Table 2.

**Table 2**

**Positive ramping slope: measured vs. calculated**

**Conclusion**

The PLL architecture is an effective approach to creating very linear ramping waveforms that are useful for radar applications. That being said, one consideration is how fast the ramp can change and still have the PLL track it. The loop filter needs to be able to allow the frequency to slew fast enough, and you need to take measures to avoid cycle slipping.

The two key results are Equations 9 and 12, which match measured results to a reasonable degree. In reality, these equations are closer to the breaking point, so you will need to add margin.

**References**

1. Banerjee, Dean. “PLL Performance, Simulation and Design, 5th Edition”, Dog Ear Publishing: 2017.

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