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Optimizing SAR ADC driver amplifier and RC filter circuit settling using SPICE

The key to obtaining the best performance on your successive-approximation-register (SAR) analog-to-digital converter (ADC) is optimizing the driver amplifier and resistor-capacitor (RC) filter front-end circuit. In this article, I’ll show you how to optimize SAR driver amplifier and RC filter settling performance by using SPICE simulations.

Figure 1 shows a typical SAR ADC driver circuit and the ADC’s internal sample-and-hold structure. SAR ADCs perform conversions in two phases: an acquisition phase followed by a conversion phase. During acquisition, sample-and-hold switch S1 closes and the external driving circuit charges the ADC’s sample-and-hold capacitor CSH to the analog input voltage.

When the acquisition phase completes, S1 opens and the ADC performs the digital code conversion using a binary search algorithm. The driver circuit must be able to completely charge CSH during the acquisition period (tacq ) and settle within one-half of the ADC’s least-significant-bit (LSB) resolution.

Figure 1

Typical SAR ADC driver circuit and ADC sample-and-hold

Typical SAR ADC driver circuit and ADC sample-and-hold

SAR ADC analog inputs are not high-impedance ports but rather present a dynamic load as the sample-and-hold switches; the current demand of the SAR input increases as a function of the sampling rate. The acquisition period on the SAR varies from device to device and in many cases is an inverse function of the sampling rate. In fast-throughput devices, the acquisition can be as low as a few dozen nanoseconds.

In the driver circuit, CFIL works as a charge bucket that helps the driver amplifier restore instantaneous charge to CSH . Choose CFIL to be many times larger than CSH to minimize the charge-kickback effect and voltage droop when the sample-and-hold switches. Use Equation 1 for CFIL :

RFIL works as an isolation resistor, helping stabilize the driving amplifier. A higher value of RFIL is helpful from an amplifier stability perspective; however, using an overly large resistor will cause settling issues, producing distortion or inaccurate conversion results. Equation 2 provides a range for RFIL given the ADC’s acquisition time (tacq ) and the LSB resolution:

Vstep is the voltage droop on CFIL when the sample-and-hold closes, typically ∼ 15mV- ∼ 100mV depending on the CFIL /CSH ratio and the sampled voltage.

The amplifier must be stable driving the capacitive load, with enough bandwidth and low closed-loop output impedance in order to charge CSH and settle during acquisition. Equation 3 shows a rule of thumb for the minimum amplifier unity-gain bandwidth (UGBW) criteria:

Equations 1-3 suggest a starting point for component selection; however, you still need to optimize the amplifier and RC filter circuit by using a circuit simulator.

Consider the fully differential amplifier (FDA) attenuator and SAR ADC acquisition system in Figure 2.

Figure 2

FDA attenuator and fully differential SAR ADC

FDA attenuator and fully differential SAR ADC

The ADC SPICE model is built using the sample-and-hold parameters taken directly from the equivalent input circuit model in the device data sheet, as well as the acquisition and conversion timing specs. Figure 3 shows the TINA-TI SPICE model for the ADS8910B.

Figure 3

Click here for larger image 
TINA-TI SPICE model for the ADS8910B sample-and-hold

TINA-TI SPICE model for the ADS8910B sample-and-hold

In Figure 3, sample-and-hold switches SW1-2 close during the 300ns acquisition period and are open during the 700ns conversion phase. Some amount of charge loss on CSH occurs during each conversion. Although the voltage across CSH does not reset in all ADCs, resetting the CSH voltage at the end of each cycle does create a conservative model for charge loss. Switches SW3-4 reset the CSH voltage to mid-scale (Vref/2) at the end of conversion. The Verror voltage probe computes the settling error in the sample-and-hold at the end of acquisition.

Table 1 shows the initial calculations for the RC filter range of values and the minimum FDA bandwidth.

Table 1

RC filter initial calculations and FDA minimum bandwidth

RC filter initial calculations and FDA minimum bandwidth

The ADS8910B data sheet recommends a filter capacitor in the range of 1.2nF < CFIL < 10nF. Due to the noise and bandwidth requirements, I chose a CFIL = 7.5nF capacitor. The THS4551 FDA (150MHz) exceeds the minimum frequency requirement.

Next, I optimized the RC values with iterations using SPICE. Figure 4 shows the TINA-TI transient results while setting CFIL = 7.5nF and performing a step parameter sweep on the RFIL /2 resistors.

Figure 4

Click here for larger image 
TINA-TI transient simulations with RFILstep parameter sweep

TINA-TI transient simulations with RFIL step parameter sweep

Figure 4 shows the CSH settling error voltage simulations. The first iteration of simulations with RFIL < 3.3 Ω show excessive ringing, while the second iteration with RFIL /2 = 3.4 Ω shows a stable and settled result with ∼ 5µV of settling error (<1/2 LSB). Therefore, selecting RFIL /2 = 3.4 Ω and CFIL = 7.5nF is an optimal RC filter for this design.

The TI Precision Labs –SAR ADC Input Driver Design video series has a detailed step-by-step explanation on to how to build your SAR ADC SPICE model and refine the RC filter values using TINA-TI software. In addition, the Analog Engineer’s Circuit Cookbook – High-Input Impedance, True Differential, Analog Front End (AFE) Attenuator Circuit for SAR ADCs shows the complete analysis and simulation files for this circuit.

Now that I’ve provided an overview of the SAR ADC’s driver transient settling simulations, you should be able to optimize and verify the settling performance of the driver circuit in a SAR acquisition system using SPICE.

2 comments on “Optimizing SAR ADC driver amplifier and RC filter circuit settling using SPICE

  1. DavidHamilton
    October 16, 2018

    It would be contradicting to be using a system that is lacking of performance. What we would like to ensure is that the circuit is fully set up in place while being in full force at the same time. Processes cannot be executed as per plan if there is a deficiency in the overall layout in any form.

  2. ChristopherJames
    February 22, 2019

    I know I can't call myself an engineer if I hate Maths, but wow I'm looking at those formulas and I'm glad that there are simpler ways to get around testing a system these days. Happy to call in other professionals to test my system for me too as long as I don't have to try and work it all out on my own! Likely I'd screw up everything because my calculations have screwed up somewhere!

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