Advertisement

Blog

Oscillator Amplitude Control, Part 1: JFET Circuit

Sine-wave oscillators such as the Wien-bridge, state-variable, or quadrature oscillators, have an inherently undefined amplitude. Ideally, the poles of their feedback loop are on the -axis and the pole-pair defining the resonant frequency has no damping. Yet in real circuits, the amplitude control by the oscillator itself is an unstable equilibrium, like a ball positioned on a rooftop peak that can roll either direction with a small perturbation in its position. In oscillators, the loop gain at the oscillating frequency must be exactly one. If it is slightly larger, the amplitude will increase exponentially, and if smaller, will undergo exponential decay.

An additional amplitude control loop stabilizes amplitude by detecting it by some means, comparing the detected amplitude to a reference voltage, and inputting the difference as an error to the forward-path (G ) amplifier. It drives a nonlinear device such as a multiplier or variable-resistance device such as a JFET, and the result of such a device is to influence the gain of the oscillator loop.

Various alternative schemes can be chosen for the amplitude control loop (ACL) functions. The peak detector can be as simple as a diode peak detector (with or without op-amp), or a synchronous rectifier, especially in oscillators with quadrature waveforms available for switching the rectifier circuit. A JFET operated in the linear region (where VDS VGS ) has a quite linear variable resistance when VDS = VGS . This is achieved by placing equal-value resistors between drain and gate and gate and voltage source, as shown below.

JFET channel resistance, rDS , varies oscillator gain. To vary rDS linearly, the vDS 2 term in the v-i equation of the JFET must be eliminated;

where the channel resistance at vGS = 0 V is

and for an n-channel JFET, IDSS > 0 A, VP < 0 V. To linearly bias the JFET, what the above scheme accomplishes is to constrain the gate-drain and gate-source voltages to be equal, or vDS = vDG + vGS = 2xvGS . The gate input circuit divide-by-2 divider satisfies this constraint, though the input, vC , is reduced also by 0.5.

Then substituting for vGS in the above JFET v-i equation,

The vDS 2 terms cancel and for the linearized circuit, the input to vGS = vC /2. The JFET channel resistance is then

The operating-point design value for the amplitude control loop forward-path output to the JFET is

For control-loop analysis in the s -domain, this circuit must be approximated by a linear approximation at an operating point. The total-variable change in channel resistance with vC is

and the fractional change in rDS with fractional change in vC is the sensitivity,

If vC changes by 20 % of VP , rDS changes by 10 %. Because rDS is infinite when vGS = VP , the range can be constrained to reduce the sensitivity of rDS (and hence oscillator gain and amplitude) by shunting rDS with a resistor, RP .

The following plot is for a PN4416 JFET with VP = –4.25 V and IDSS = 10 mA. The solid plot is that of rDS and the dotted curve is of RP in parallel with rDS . The combined resistance is RP when vGS = VP , and RP is asymptotically approached as rDS asymptotically approaches infinity.

The resistance presented to the oscillator circuit branch has a maximum of RP and is constrained to a desired design range of

This “gain” has the units of 1/A and might be better expressed on a plot as negative current, as shown below.

The above plot is semilog, and the slope, which is the needed gain for ACL analysis, is obviously not constant. Consequently, the choice of operating-point will significantly affect the ACL gain and dynamic response. An op-pt chosen near VP has high gain and also high nonlinearity, though RP provides some linearization while reducing gain. For a change in vGS , this is the resulting JFET current, iD , around the operating-point of VGS . For design, an estimate is made of the resistance range needed for rout and the above formulas worked backwards to give a quiescent vGS = VGS . For a given type of JFET (with VP and IDSS then known), vC = VC can be found from the preceding equation that takes into account the attenuation, vGS /vC = 0.5.

The transfer function for this nonlinear block in the ACL is linearized at an operating-point of VC and rout0 at which the incremental gain, including the ×0.5 input divider, is

1 comment on “Oscillator Amplitude Control, Part 1: JFET Circuit

  1. rockcjapple
    May 3, 2015

    thanks for this info .

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.