Overcoming verification tool limitations for analog/RF designs

Insatiable consumer demand, multi-GHz communications, and nanometer-scale process technologies are driving a pervasive need for high-complexity, high-frequency analog and RF circuitry. Designers have risen to the challenge with new architectures and innovative circuit techniques, yet their verification tools have fallen sorely behind.

Complexity has increased many orders of magnitude over the last 20 years, but SPICE simulators have not kept up. RF simulators enable faster periodic analysis, but have severe limitations handling today's increasingly complex nonlinear circuits. Since neither tool can adequately verify multi-block or full-circuit designs, designers have had to improvise with mixed-level simulators, FastSPICE simulators, and test chips, each of which comes with significant penalties in terms of time, effort, and accuracy. The result is higher design costs, longer schedules, silicon respins, and over-design.

A New Class of Verification Problems
IC development schedules include extra weeks and months for verifying difficult potential problems such as large-circuit DC convergence, highly nonlinear periodic steady-stage (PSS) convergence, week-long transient runs, voltage-controlled oscillator (VCO) and phase-lock loop (PLL) phase-noise analysis, multi-block interconnect validation, post-layout verification, and corner analysis. The number of silicon test chips and respins directly related to such issues are a poignant and highly visible measure of the problem, especially when masks for nanometer-scale devices are more than $1M each.

Less obvious, but just as real, is the loss in potential performance, power, area, and integration that designers are leaving on the table because they do not have adequate tools to analyze their circuits with silicon accuracy.

The reason for these problems is clear: today's analog/RF circuits bear little resemblance to circuits just a decade ago, yet simulator technology is largely unchanged. Consider the following list of circuit characteristics, all of which have emerged as major concerns within the past decade yet have not been adequately addressed in traditional analog/RF verification tools:

  1. Complexity: circuits with >100,000 analog/RF transistors.
  2. Process: nanometer-scale complementary metal”oxide”semiconductor (CMOS).
  3. Frequency: up to multiple GHz in standard CMOS.
  4. Multi-rate: frequencies dispersed many orders of magnitude.
  5. Nonlinearities: hard switching in transceivers and low power circuits.
  6. Power: low voltages driving extreme signal-to-noise ratio requirements.
  7. Noise: device and flicker noise as first-order effects.
  8. Variability: inter- and intra-die variations driving architectural enhancements.
  9. High-Q: increasing use of crystal oscillators with high-Q factors.
  10. Parasitics: vastly grown in number and impact on circuit performance.

The problem is not so much any given characteristic above. It is that most of today's advanced circuits include many, if not all, of these characteristics simultaneously.

Limitations of Traditional Circuit Simulators
Design teams applying traditional simulators to leading-edge verification problems must constantly ask themselves how to accurately verify their design as quickly as possible. The answer is becoming more difficult with more complex designs. Designers would like to be able to run full-accuracy simulations on large designs with reasonable runtimes and without any special modeling or tuning. Transient, full-accuracy simulation requires a traditional SPICE simulator, but SPICE runtimes have become increasingly impractical for GHz circuits implemented in nanometer-scale silicon.

Design teams generally structure their tasks around expected simulation runtimes. A daytime run generally take up to two hours to analyze and verify blocks. An overnight run takes a nominal 12 hours, to verify complex blocks and simple multi-block circuits. Weekend runs tend to last 60 hours, verifying multi-block circuits, post-layout blocks and simple corners (PVT), and special cases such as PLL locking. Extended runs last nominally up to a week, verifying complex multi-blocks (e.g., full transceiver), post-layout multi-blocks, extensive corners, and critical cases such as long PLL locking.

No design team can simply allow daytime tasks to require an overnight run, overnight tasks to require a weekend run, weekend tasks to require extended runs, or extended runs that become infeasible. Instead, they find other methods that let them get their job done, albeit at the expense of accuracy and productivity.

SPICE Simulator Limitations
The most obvious method to address the full-accuracy simulation runtime problem is to partition circuits into smaller blocks, e.g., adding a level of hierarchy. While this can get block-level runtimes to acceptable levels at full accuracy, the result is significant lost productivity in partitioning, testbench creation, simulation, and analysis for many additional blocks.

This approach does not address the multi-block runtime problem. In fact, it makes it worse because the design team very often needs to perform an additional level of multi-block simulation due to the additional hierarchy. Moreover, designers do most of their optimization at the block level, in part because they require fast simulation iterations in order to tweak their circuits. Creating smaller blocks makes it much more difficult to optimize the overall circuit and, therefore, less likely that designers will do so.

Transient runtimes are not the only problems for today's SPICE simulators. Design teams need to perform DC analysis to check for correct power behavior, excess leakage currents, excess power dissipation, and related issues. DC convergence has become a difficult-to-impossible task for many complex circuits. Designers are accustomed to using increasingly elaborate and time-consuming procedures to get DC operating points, including making minor circuit changes (e.g., eliminating small floating resistors and simplifying models), providing extensive node estimates, changing simulation parameters (e.g., iteration limit and step size), loosening tolerances, ramping voltages using transient, and partitioning the design.

These approaches are time consuming and can help only so much. Unable to perform DC analysis in simulation, design teams increasingly have to risk going to silicon anyway.

Mixed-level Simulator Limitations
Many design teams have taken to using mixed-level simulation to augment circuit-level simulation. This offers many benefits, including efficient, early system-level analysis and a flexible, realistic testbench environment for block and multi-block circuit simulation. While this approach obviously does nothing to address the block-level SPICE runtime issues, it holds the promise of addressing multi-block runtimes if the block-level behavioral models are accurate enough.

However, creating and maintaining accurate models can be tricky, time consuming, and error prone. The required and actual levels of accuracy are very difficult to determine, and the act of increasing model accuracy itself requires ever increasing time and effort. For these reasons, circuit designers generally trust models only for system-level analysis and functional testing. They know that the only way to guarantee SPICE accuracy is to simulate the circuit itself.

FastSPICE Simulator Limitations
A third alternative, FastSPICE simulation, sacrifices both circuit and simulator accuracy in order to increase performance. FastSPICE often provides orders-of-magnitude speedup versus SPICE in digital applications, and its accuracy is good enough for such applications. However, FastSPICE simulators get this speedup by using simplifying assumptions and approximations that sacrifice accuracy that is essential to analog and RF applications.

These simplifications include partitioning, using alternative device models (e.g., table lookup or piecewise-linear models), evaluating based on events, device and circuit approximations (e.g., grounding floating capacitors and inductor approximations), and eliminating time-step convergence and truncation error checking. Such simplifications can result in grossly incorrect behavior if not properly managed.

Applying FastSPICE to analog and RF designs requires tuning the simulator accuracy to each individual block, in order to get the highest performance, while maintaining reasonable circuit behavior. Of course, there is always a risk that apparently accurate-enough block behavior will lead to completely inaccurate full-circuit behavior, especially for designs that have complex feedback paths.

Nevertheless, many design teams use FastSPICE for long simulations in which accuracy is not paramount, e.g., functional multi-block connectivity. In such applications, designers often spend multiple weeks in block-level FastSPICE tuning. Successful tuning requires good understanding of the entire circuit. Empirically, the result is typically 3 to 5 times faster simulation than SPICE for applications that are not accuracy-sensitive. Despite the high setup costs and low accuracy, FastSPICE simulation has enabled designers to verify functional behavior that would not otherwise be visible until silicon.

FastSPICE simulators' inherent inaccuracy fundamentally limits its applications in analog and RF designs. FastSPICE simulations can perform only basic functional verification. Its results are not accurate enough for performance analysis (e.g., meaningful node or specification measurements).

Consider the simulation of an A/D converter. Tuning a FastSPICE simulator to within 1% of SPICE while maintaining a reasonable performance advantage is difficult. At that accuracy, the simulator can verify only the first six significant bits of connectivity; bits seven and beyond are masked by the simulator inaccuracy. FastSPICE simulators have proven unable to provide the accuracy needed for performance simulations (e.g., simulations in which specification or node measurements are critical). Moreover, tuning a FastSPICE simulator to near-SPICE accuracy generally results in slower performance than SPICE.

RF Simulator Limitations

Many design teams begin using RF simulators specifically in order to perform VCO phase-noise analysis. Again, the simulators have not kept up with the problem. RF simulators use linear approximations to calculate noise. However, accurate phase-noise characterization for VCOs and PLLs requires a nonlinear analysis that present RF simulators do not provide. This produces non-physical results such as infinite total power in an oscillator.

For PLLs, the standard approach is to use RF simulation to get block-level estimates, and then create top-level behavioral models to calculate the overall noise. This approach produced acceptably accurate results for MHz circuits at 0.25 microns. However today's multi-GHz wireless, wireline, and high-speed I/O standards have critically tight phase noise and jitter specifications. The present approach has proven to be grossly inaccurate at low-offset and high-offset frequencies for the nanometer-scale, GHz circuits needed to meet these specifications.

Convergence problems are not unique to DC analysis. PSS convergence is an even bigger problem for high-frequency analog and RF designs. Today's RF simulators are notoriously poor at PSS convergence. Again, the increasingly elaborate procedures only take designers so far. At the limit, designers must further partition their design wherever possible, thereby incurring extra time and effort, and risk missing problems between blocks. Where partitioning is not possible or cost-effective, circuit designers again end up using increasingly expensive silicon to verify their circuit.

Multi-rate circuits are another difficult problem for today's simulators. The issue is how to efficiently simulate circuits with frequencies that are either greatly disparate (carrier and modulation) or closely matched (producing a low beat frequency). SPICE simulators require time-step rates based on the highest-frequency signal, yet need to run long enough for the lowest-frequency signal. This often results in infeasible, multi-week transient runs.

Harmonic balance analysis is an attractive alternative for mildly nonlinear circuits. However, harmonic balance rapidly becomes impractical with increasing circuit nonlinearity and size; the simulator grinds to a crawl or runs out of memory when it needs to include hundreds of harmonics in order to achieve convergence or maintain accuracy.

Quasi-periodic steady state (QPSS) analysis has been another practical alternative in some cases. However, as implemented in current simulators, it suffers from many of the same limitations cited above for PSS analysis. It is often feasible to apply only one large signal and one or two moderate signals, which is not sufficient to fully characterize many specifications of interest (e.g., blocker analysis and receiver sensitivity).

Simulator Limitations Summary
There are many problems in addition to those mentioned above, from post-layout verification to extensive corner and configuration verification. Yet the pattern is clear: Simulation capabilities (performance, convergence, and analysis) have not kept up with increasingly demanding verification needs. Using time, effort, and considerable ingenuity, designers have pushed the technology far past what the simulators' original developers ever contemplated. Design teams have come up with alternative approaches using mixed-level simulation, FastSPICE simulation, and even test chips to push the limits even further.

However, they have hit the breaking point for a large and growing number of applications. Design teams increasingly face taking circuits with known high risks directly to silicon and then dealing with the nightmare scenario of silicon that misses a critical specification not by some gross amount that they have a chance of diagnosing, but by 1 dB or 1 ps, which are problems that require full-accuracy, full-circuit verification before tapeout.

Filling the gap between traditional circuit simulation and silicon
An alternative exists to fill the growing gap between traditional circuit simulation and silicon for leading-edge analog and RF designs. Called Precision Circuit Analysis (PCA), it combines innovative applied mathematics with advanced numerical optimization techniques to deliver full-SPICE accuracy transient and periodic analysis that is five to ten times faster than SPICE, with no block-level tuning (Figure 1 ).

Figure 1: Full-SPICE accuracy, 5x-10x faster, no tuning.

Precision Circuit Analysis technology is based on a proprietary combination of innovative applied mathematics and numerical analysis techniques optimized to every component in the simulator. The development team followed one simple rule: never compromise accuracy, and then get as much performance as possible.

Design teams have used Precision Circuit Analysis to verify a wide range of designs including wireless transceivers, wireline transceivers, high-speed I/Os, power regulators, sigma-delta ADCs, memory interfaces, and multi-GHz PLLs and DLLs. PCA transient analysis delivers identical results to traditional SPICE tools, but does so with five to ten times higher performance, and with vastly superior DC convergence.

By solving the original device equations without any approximations, abstractions, or short cuts, the tool delivers identical waveforms as traditional SPICE simulators at every node on every run. Similarly, PCA RF analysis delivers breakthrough PSS convergence and 5x-10x faster periodic analysis for highly nonlinear single-block and multi-block RF circuits. PCA technology also solves the notoriously difficult PLL phase noise analysis problem, delivering closed-loop, non-approximate phase noise analysis for integer-N PLLs with silicon-validated relative accuracy to within 1dB.

Consider the following representative examples:

  • Automatic Gain Control with bandgap & bias ( ≈16K elements)
    • 36X —SPICE: >13 hours, PCA: 22 minutes
  • Sigma-Delta ADC (total elements: ≈15K)
    • 12X —SPICE: 41 hours, PCA: 3.3 hours
  • PLL ( ≈6.4K elements, ≈5.6K MOS)
    • 6.7X —SPICE: 70 hrs, PCA: 10.5 hrs
  • Frequency Synthesizer ( ≈10.5K elements, ≈5K MOS)
    • 9.7X —SPICE: 8.5 days, PCA: 0.9 days
  • 802.11 TxRx (>250K elements, ≈200K MOS)
    • N/A —SPICE: could not converge, PCA: DC convergence <2 hrs
  • SRAM (>1.1M elements)
    • N/A —SPICE: did not complete, PCA: 1.2 hours
  • Top-level Receiver ( ≈75K elements, ≈11K MOS)
    • 6X —SPICE: 220 hrs, PCA: 35.6 hrs (6x)

Just as with every technology, Precision Circuit Analysis has its limitations. PCA delivers superior performance by taking advantage of computational efficiencies for circuits with large number of devices, complex devices, strong nonlinearities, and widely disparate frequencies (multi-rate).

Runtime is a good first-order indicator of computation complexity. PCA consistently delivers performance gains of better than 5x, compared to traditional SPICE for transient simulations which run over one hour. It delivers more modest performance gains for shorter simulations. In order to deliver full SPICE accuracy, Precision Circuit Analysis runs circuits flat, i.e., without any type of hierarchical redundancy.

This means that it is not practical for simulating large SoCs at a transistor level. The PCA “load capacity” is similar or slightly better than traditional SPICE simulators. However, its vastly superior convergence and runtime give it a much higher “effective capacity.” Whereas traditional SPICE simulators are generally practical for circuits with up to perhaps 100K total devices, PCA readily handles circuits with over 1 million devices.

Market drivers and technical enablers are pushing advanced analog and RF circuits to new levels of complexity, multi-GHz frequencies, and nanometer process technologies. Combined with increasingly challenging physical characteristics such as highly nonlinear multi-rate circuits with high-Q factors, the result is a new class of verification problems that traditional SPICE, RF, FastSPICE, and mixed-level simulation simply cannot handle effectively. With considerable time, effort, and ingenuity, designers have pushed these simulators beyond all reasonable limits.

Fortunately, new technology now enables designers to analyze and verify circuits that would otherwise be impractical or infeasible. For full transceiver-performance simulations, DC convergence of >1M element post-layout circuits; silicon-accurate multi-GHz, nanometer, VCO noise analysis; and extensive high-speed, I/O corner analysis, designers no longer have to work around limitations or tape out with inefficient margins, with technology that delivers full accuracy with much higher performance.

About the author
Paul Estrada is Chief Operating Officer at Berkeley Design Automation, Berkeley, CA. His prior experience includes executive positions at Cadence, 0-In Design Automation, and Synopsys. He has engineering degrees with honors from Stanford University and University of Illinois, and holds three patents.

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