The power-performance-area (PPA) metric and time-to-market of modern system-on-chips (SoCs) are dominated by two major issues: on-chip interconnects and layout parasitics. Especially, as the industry migrates to FinFET technologies, IC layout parasitics has become the dominant source of performance and reliability bottlenecks.
Parasitics—the unintended elements in IC designs that degrade circuit performance, precision, and power efficiency—is crucial in SoCs vying for higher density, faster speed, and greater precision along with the continued migration to more advanced technology nodes. These parasitic elements are responsible for bottlenecks, choke points and weak areas that affect IC performance, power efficiency, robustness, and reliability.
On the other hand, debugging the design problems and addressing the underlying issues caused by these problems have become difficult, tedious, and time-consuming. Diakopto, a supplier of visualization and optimization tools for complex IC designs with the primary focus on layout parasitics, claims to have an answer to the problem of very large power grids in SoCs with high-performance analog circuitry.
ParagonX—which assists engineers in parasitics debugging of analog, mixed-signal, and custom digital IC designs—visually pinpoints the few critical parasitic elements responsible for bottlenecks, choke points, and weak areas. That, in turn, reduces parasitics-related IC debugging and optimization time from days or weeks to minutes or hours. It’s a highly valuable advantage during the tapeout phase.
Figure 1 ParagonX helps IC design and layout engineers to quickly and easily find root causes of the parasitics-induced design problems. Source: Diakopto
Michael Kappes, CEO of IQ-Analog, acknowledges that ParagonX has enabled his company’s engineers to quickly and easily pinpoint bottlenecks and root causes of IC design challenges caused by layout parasitics. IQ-Analog is a developer of wideband transceivers for 5G wireless systems.
Another semiconductor outfit that has employed ParagonX to find and fix a broad range of IC problems caused by layout parasitics is Alphawave, a multi-standard DSP-based connectivity IP supplier. Alphawave’s CEO Tony Pialis says that ParagonX quickly pinpoints layout issues and bottlenecks and that the analysis of small blocks is immediate. More importantly, he notes, it analyzes very large netlists that are impractical to simulate using other tools without compromising accuracy. “The large capacity of ParagonX allows Alphawave to accurately validate key electrical targets at the top level of integration and iterate quickly.”
Then there is Analog Circuit Works, a chip design services firm that helps SoC developers integrate the analog electronics interfacing everything from actuators, sensors and imaging arrays to cables, antennas and backplanes. Bill Ellersick, founder and CEO of Analog Circuit Works, said that engineers at his company were up and running with very little training, and they were quickly able to find and fix problems caused by parasitics.
Figure 2 ParagonX provides intuitive results and deep insights into parasitics-induced problems. Diakopto
ParagonX features a set of tools for rapid resistive, capacitive, delay, structural, connectivity, and net-matching analysis and visualization. It shows the most and least critical areas to be fixed on the circuit layout, allowing engineers to make necessary tradeoffs among performance, power, and area.
The San Jose, California-based Diakopto claims that over 30 semiconductor industry outfits have adopted its debugging and design optimization platform. The ParagonX platform has been employed to analyze and optimize a broad array of IC designs. That includes high-speed SerDes, high-precision data converters, RF, image sensors, power management, custom memories, optical transceivers, low-power IoT, silicon photonics, memory PHY, and general-purpose analog.
Majeed Ahmad, Editor-in-Chief of EDN and Planet Analog, has covered the electronics design industry for more than two decades.
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