# Parasitics & Capacitor Selection, Part 1A: Leakage

Essentially, every capacitor comes with a free resistor and inductor (at the very least). Loosely termed the parasitics, these elements affect capacitor performance, causing real values to depart from those recorded using perfect theoretical models. As such, parasitics often play a greater role in determining the suitability of a capacitor for a given application than the actual nameplate capacitance value of the part itself. One parasitic element to consider when selecting a capacitor is leakage.

The ideal capacitor is a perfect open circuit with respect to DC. However, the dielectric insulator, which increases the field between the plates, has intrinsic microscopic conduction paths between the plates. Each acts as a small parallel resistor in the circuit. The paths allow current to flow but also result in direct current leakage (DCL), one of the many parasitic elements that must be considered when selecting and specifying capacitors.

Each dielectric type has its own intrinsic resistance characteristic per unit surface area of the dielectric, which allows current to leak across the capacitor plates. In finished capacitors, we often specify the sum of these as DCL for a given rating. It's imperative to control the overall leakage in many practical applications, but it's especially important in portable electronic devices (i.e., any handheld electronic device with a battery). Having spent many years working with various capacitor families, I find it useful to characterize DCL by visualizing capacitors as buckets with a hole. The fluid in the bucket represents the amount of charge the capacitor is carrying and the properties of the various dielectric materials comprising it. In this context, leakage can be evaluated by answering two simple questions:

• If the bucket is only half full, does the leak flow faster or slower?
• If the temperature increases, how will that affect the flow?

Keep these questions in mind; we'll come back to them later. Before delving too much deeper, though, let's make sure we have a basic understanding of the leakage current limits for different technologies.

Let's revisit the conduction paths intrinsic to the dielectric insulator. As a first order, it's important to consider them evenly distributed. If you doubled the surface area of the plates for a given dielectric thickness, you'd double the number of sites and the leakage current. You would also double the capacitance, because there is a linear relationship between DCL and capacitance. Alternatively, if you doubled the dielectric thickness but kept the surface area and number of paths the same, you'd double the voltage rating and maintain the same leakage current, but you would halve the capacitance. To maintain the original capacitance at double the rated voltage, you would need to double the plate area. However, as we just noted, doubling the plate area doubles the original leakage current, which means that DCL is also a linear function of voltage rating.

This is actually very convenient. It means that DCL limits can be calculated directly as a ratio of capacitance and voltage ratings. For example, to calculate the DCL limit in microamps (µA) for tantalum technology, you multiply the capacitance in microfarads by volts by 0.01: DCL limit = 0.01C*V. This same trend holds true for aluminum dielectrics (though it's actually a function of the square root of CV) but with a larger ratio reflecting typical leakages in milliamps (mA), rather than microamps.

In the case of ceramic and film capacitors, parallel resistance is expressed as insulation resistance (IR) and is directly related to leakage current by Ohm's Law. In these technologies, the typical IR is measured in mega-ohms (MΩ) or giga-ohms {GΩ), which results in extremely low leakage measured in nanoamps (nA). However, due to the linear relationship between DCL and capacitance, IR specifications are typically expressed in terms of a MΩ minimum (1000MΩ) multiplied by the capacitance value in microfarads (µF): IR = 1000MΩ*C.

If we were to set all the different capacitor technologies' intrinsic limits on a common scale (let's take IR for a 1.0uF/10V rating), the IR range (for which larger values are better) would be 105MΩ for NP0 ceramics and polypropylene film capacitors, 104 MΩ for X7R ceramic and polyester film capacitors, 102 MΩ for solid tantalum capacitors, and 1 MΩ for aluminum electrolytic capacitors.

These equations and values are theoretically sound and provide accurate specification limits, but what happens in the real world? In Part 1B, we will finish our discussion of leakage with a discussion on the DCL limit, voltage and temperature effects, and DC measurements.

## 3 comments on “Parasitics & Capacitor Selection, Part 1A: Leakage”

1. etnapowers
February 28, 2014

“However, the dielectric insulator, which increases the field between the plates, has intrinsic microscopic conduction paths between the plates”

It depends on the particular dielectric inserted between the plates, and it depends also on the technology of deposition of the dielectric material, and on the trapped charges inside the oxide.

2. Chris-R
May 28, 2014

Correct – there are many factors here including how the dielectric is prepared and its rsultant purity (ppm or ppb level of any conductive inclusions).

3. etnapowers
June 12, 2014

@Chris, I add that also the packaging process of the capacitor might influence the microscopic conduction paths between the plates.

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