Phase- and Delay-Locked Loop Clock Control in Digital Systems

Synchronous sequential systems rely on
globally synchronized clocks. With the increase in clock rates,
low-skew clock distributions are becoming increasingly critical to
achieving design speed objectives. High-speed circuits may also
require clocks with programmable duty cycle and delay. For all
these applications, we must employ a comprehensive clock management
on a chip. The Phase- and Delay-Locked Loops are used to achieve
low clock skew distributions. The principles of frequency
synthesis, by which the clock rates can be multiplied and divided,
are outlined, together with its applications. We then focus on the
correct design of the PLL/DLL building blocks. These include the
voltage-controlled oscillators (VCOs) that employ delay elements,
phase and frequency detectors, and, the loop filters that make the
control feasible. The study concludes with the outline of patented
solutions to scalable, robust, and technology-independent solutions
for future clock managers.

Closed-Loop Clock Skew Suppression

The basic idea of the active closed-loop clock skew compensation
is to reduce exactly as much clock skew as needed. This is achieved
by using the circuitry that can generate a clock signal, or
modulate its delay. Typically, such compensation is placed in
incoming clock buffers. The overall effect is equivalent to that of
inserting the negative delay in the clock path. Note that any of
the passive techniques for reducing clock skew with layout and
clock network speed optimizations cannot completely reduce the
clock skew. Only the use of the closed-loop clock skew reduction
can lead to that goal.

Figure 1:  Two closed-loop clock distributions.
(a) PLL and (b) DLL

The active skew compensation can be achieved by using either
PLLs or DLLs. Both compare the input and feedback clocks, and
guarantee that they are aligned. The difference between the two is
in the use of the internal delay line.

In DLLs, the delay line inserts the controlled delay between the
input and output clock. In PLLs, the delay line is used as a ring
oscillator that is realized by closing the loop and guaranteeing
that the inverted output of the delay line is fed back. Hence,
while DLLs only delay the incoming clock signals, the PLLs actually
generate a new clock signal in such a way that the delay in the
clock distribution is completely eliminated.

In addition to aligning clock signals, PLLs can synthesize
frequencies. To achieve clock division, it is sufficient to place a
divider in the incoming clock path; in other words, PLLs are not
necessary to perform divisions. Multiplying clock rates, on the
other hand, generally cannot be done without using the PLL
closed-loop control. Since PLLs adjust the internally generated
clock rate to that of the input clock, you can only achieve the
stable-state solution if the generated clock is multiplied.

Realizing PLL/DLL Building Blocks

A VCO is the basic element of a PLL. The VCO generates the
clocks whose rates depend on an input control voltage. Ideally, the
clock rate is proportional—linear to the control voltage. For
digital circuits, the clock is a square wave realized by connecting
discrete delay elements into a ring oscillator. Required
characteristics include low jitter of the generated clock and high
immunity to externally induced noise.

Delay Elements
You can realize the delay line used in PLLs or DLLs used for clock
distribution purposes in two ways. Both realizations use CMOS
inverters connected in series. The delay in each inverter is
controlled by the input control voltage.

Current-Starved Inverter Lines vs. Capacitor Loaded

The current-starved delay line consists of a series of inverters.
The delay through each inverter is controlled by the amount of
current that is allowed to pass. For that purpose,
voltage-controlled resistors are inserted in inverters, between the
NMOS and PMOS transistors. One such implementation realizes the
resistors with a complementary transistor pair whose gate voltages
are self-biased by complementary current mirrors. Based on the
input control voltage applied to the NMOS transistor gates, the
complementary PMOS gate voltages come from the gate voltage of the
PMOS transistor in the input mirror.

The capacitor-loaded delay line adds capacitors to the output of
each inverter. The capacitance discharge is then dependent on the
control voltage. One way of achieving this goal employs a serially
connected resistor, similar to the previous case.

The delay range in the VCO depends on the minimum and maximum
delays in each element, and on the number of delay elements. The
VCO control voltage controls the delay in each delay element. The
exact relation depends on whether the delay line is current-starved
or capacitor-loaded. In the former case, the transfer function is
monotonically decreasing, while in the latter it increases
monotonically. Semiconductor-process variations can slightly alter
transfer characteristics—in general, there will be more spread
from the capacitor-loaded elements, which implies that the
current-starved implementations are better.

Another point worth noticing is that you can extend the
clock-rate range of a VCO by changing the delay-line
length—the number of elements by adding taps to each inverter.
Practical realization of such VCOs is simple and requires the
addition of a single multiplexer that chooses the delay line

Jitter Reduction Through Noise Reduction
To reduce the clock jitter induced by external noise, the delay
line should possess good noise rejection properties. In a simple
model, the noise is added to the power supply and the delay through
an inverter is then expressed in terms of the power supply voltage.
Using the same approach, you can express the sensitivity of the
complete delay line, including the delay-control elements.

To protect the circuit from the delay variations that cause
clock jitter, reduce noise through the power supply. Either passive
or active methods can reduce the power supply noise. The passive
methods employ filters on the power supply lines. The active
methods achieve better protection by regulating the power supply.
On-chip power regulators are usually of linear design. Linear
regulators include a feedback control loop that keeps the voltage
constant. In practice, such regulators significantly reduce the
power supply noise, typically between 30 and 80 dB. However,
standard operational-amplifier feedback-loop stabilization is
critical to achieving correct linear operation.

In situations where you cannot effectively reduce the noise, or
where additional tolerance is needed, use differential delay
elements. The simplest such implementation consists of two parallel
inverter chains. The elements in one chain carry the signals of the
polarity opposite to the corresponding elements in the second. The
delay control circuitry is replicated as well. To save the space,
you can merge both inverter chains in a delay line that includes
the delay control circuits as well.

Phase Comparators
Phase comparators are the second major elements of PLLs/DLLs. Their
role is to detect the phase or frequency difference between the two
compared clocks. The phase information is used to generate the VCO
control signal.

Several implementations are possible. The simplest
implementation consists of a single XOR gate that generates the
Boolean difference between the two clocks. The difficulty with this
implementation is in the exact interpretation of the

Sequential implementation consists of a single flip-flop. Here,
one input (B) is used as a clock signal. The other input (A) is
then latched into a flip-flop at every positive edge. If the edge
of the first input arrives first, zero is latched. Otherwise the
flip-flop latches the value of logic one. The output value then
uniquely determines if the delay line should be sped up or slowed
down. This value is regenerated at each positive clock edge of the
first input.

Best suited are detectors that compare both the phase and the
frequency of the two inputs. These comparators are referred to as
the phase-frequency detectors. They consist of two flip-flops
clocked by different clock inputs. The first flip-flop to be
clocked produces the logic-one output, and resets the other
flip-flop. When the clock edge of the second clock arrives, the
second flip-flop shortly outputs the logic one, and both flip-flops
are reset. The overall effect is that, between the positive edges
of the two inputs, either the signal for speeding up or slowing
down the VCO is active.

You can represent the detector as a three-state finite-state
machine. The signal states that the VCO should speed up, slow down,
or perform as before. The examples of the detector executions
illustrate the operation of the phase-frequency detector. When the
feedback signal lags the input clock, the VCO should speed up,
otherwise it should slow down. In the locked state, when both edges
coincide, both detector outputs become active for a short period of
time. The durations of the two outputs are the same to achieve low

PLL Stability
Proper filters are used to stabilize the control of the PLL. This
is the stability problem similar to the problems in any closed-loop
control systems. In the case of PLL control, the state signals are
the phase difference, the VCO control voltage and the output
frequency. Exact analyses are possible by various simplified
models. The transfer function includes the filter components and
you get stability analysis using the usual closed-loop
stabilization techniques. The required filter can be implemented as
passive or active. The exact form of the filter depends on the
implementation of each element of a PLL.

The most common form of a PLL uses a charge pump, consisting of
a capacitor and the switches that either charge or discharge the
capacitor. The charge pump PLL consists of a phase-frequency
detector, a charge pump, and a delay line VCO. The two outputs of
the phase frequency comparators control the charge accumulated on a
capacitor, and consequence the VCO control voltage. Relatively
simple passive filters are sufficient to achieve loop stability.
Simple rules of thumb have been used in filter design since the
early days of charge pump PLLs.

DLL implementations can achieve stability by simpler means, as
no internal feedback loop exists. However, many difficulties can
mar the practical implementations. Since DLLs employ the controlled
delay line, their correct operation requires that the delay is
exactly one clock period. It is possible to have situations in
which zero periods, two periods, or any even-integer multiple of
the periods are possible. In general, the recognition of such false
locks is difficult, and relatively complex digital circuitry might
resolve the false locking problem. Some applications of DLLs might
require the turbo mode in which the lock is acquired quickly,
sometimes in one clock cycle. A class of DLLs uses the bang-bang
controllers that quickly and accurately achieve the locking

Industrial Clock Managers

The ORCA FPGA clock manager from Lucent Technologies is an
example of a complex clock manager. You can program the clock manager in several PLL
or DLL modes. The program configuration is loaded into eight
registers. The register outputs control the operation mode. Several
sets of switches configure the clock manager. The switches select
between the PLL and DLL mode; determine the loop length; and route
the input, feedback, and two output clocks. In addition, three
dividers are placed to allow the clock synthesis of two independent
clock outputs. In PLL modes, you can achieve frequency synthesis,
while in DLL modes, you can achieve the delay and the duty cycle
adjustment. Since frequency synthesis is, in general, not feasible
by DLLs, one more operation provides the doubled output clock

Systems where clock rates change during chip operation may
require dynamic clock management. The recent introduction of
Transmeta processors demonstrates the low-power benefits of such

For a number of reasons, dynamic clock control will not work
properly just with ordinary clock managers. First, clock division and multiplication requires
the use of clock dividers—current dividers cannot do this
operation. Second, the rest of the clock manager, including the VCO
and loop filters might not work properly during the dynamic clock

Clock dividers, when used dynamically, introduce a series of
problems. Under some conditions, the forbidden states of the
divider are introduced, causing undesired cycle lengths, irregular
clocks, and oscillations at clock rates that are too high for the
rest of the sequential system. In addition, even if the divider
will eventually work properly, there might be transient states
during which the clock outputs are unsafe. Remember that under no
circumstances can the clock signals exhibit glitches. Our
patent-pending dynamic clock divider protects against all these effects. Similarly,
our patent-pending VCO design is optimized for dynamic clock
management applications , their scalability to high bandwidths, low
voltage, and their easy use in programmable systems.

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