Pick Your SPICE Models Carefully

While the basic simulation program with integrated circuit emphasis (SPICE) hasn't changed over the past 40 years, the simulation models for metal-oxide-semiconductor field-effect transistors (MOSFETs) have undergone substantial change.

Despite modeling improvements, analog designers who use manufacturer SPICE models for PCB work have not always benefited from these advances. Some consequences of using older simulation models are that the accuracy of simulations will suffer and the ability to even simulate a circuit might not be possible. I thought it might be helpful if I could share some insight into things to watch out for to avoid the headaches.

MOSFET models have traditionally been referred to by their level. For example, originally MOSFET models were called Level 1, Level 2, or Level 3. I am surprised that these outdated model types are still supplied by companies selling discrete power MOSFETs given all the problems they exhibit.

The Level 1 through Level 3 models employ many of the generally accepted current versus voltage (I-V) equations one would see in a textbook. The problem with these models is they don't describe the I-V relationships with one continuous equation and are not always monotonic (i.e., exhibit negative resistance!). This can lead to convergence problems when simulating. To understand why requires understanding a subtle aspect of how a SPICE simulator arrives at solution points in a transient or dc analysis.

Anyone who has studied differential calculus knows that derivatives don't exist at the discontinuity point in an equation. Think of an ideal square wave signal with zero rise time. The slope changes from zero to infinity at the point the voltage starts to rise. This is a discontinuity. While this doesn't happen in a real digital circuit, it does happen when a Level 1, 2, or 3 MOSFET SPICE model is used as SPICE tries to solve the I-V equations on the cusp of going from the linear operation mode — one equation — into the current source mode: a second equation.

If SPICE tries to solve a simulation point around a discontinuity it will fail to converge. The solution will oscillate between both sides of the discontinuity until the iteration variable, ITL1, is exhausted and the simulator stops. This is probably the most aggravating part in simulating circuits using SPICE.

With the advent of BSIM models 1 and 2 from the University of California at Berkeley, non-physical fudge factors were introduced to smooth the IV transition from one region of operation to another. While there were still cases where discontinuities crept in, at least by BSIM 3 the convergence problems were greatly diminished. BSIM 3v3 is still a very popular simulation model because of its good convergence characteristics and accuracy for moderately small geometry devices.

Today, MOSFET SPICE models are more frequently referred to by names like BSIM4, BSIM5, PSP, HiSIM, EPFL-EKV, etc., although many simulators still force those names to a Level number. For example, HSPICE calls their BSIM 3v3 model Level 49. Each of these models addresses the simulation problem from different perspectives.

In 2005, the Compact Models Council (CMC), a working group established in 1996 to decide the fates of all model types, voted out the BSIM model for their recommended future standard. The 65nm and below modeling “hat” was passed over to the PSP model team from Penn State University (now supported by Arizona State University) and the then Philips Semiconductor (now NXP). The vote was a clear majority (written with a smile) of 17 to 14. Actually, it came down more to simulation speed, capacity, and logistics; how the model would be distributed (e.g., Verilog-A code versus C code). Anybody who has tracked SPICE simulation speed claims can just imagine the fight trying to have 31 people agree on a test circuit to prove simulation speed winners.

But 65nm is not something most PCB designers need to worry about for awhile. Rather, if you can work with vendors that supply BSIM models version 3 or later, you will minimize the headaches during simulation. When working with power MOSFETs, it is even better if your vendor has a simulation sub-circuit model that includes package parasitics along with the transistor.

Analog semiconductor companies don't routinely use a simple BSIM-only model for simulating power transistors. Typically their models are elaborate sub-circuits with other modeled components around the device like JFETs to model voltage-dependent drain resistance. More recently they also use tools such as R3D from Silicon Frontline to extract complex 2D and 3D on-resistance and turn-on delay timing. If the models use these extracted features, they are very precise, and more importantly, enable the study of EMI issues related to power FET rise-fall times and Joule heating — extremely important issues when dealing with high-power voltage or current transients.

The ability to simulate a circuit with SPICE before building a board is important if the design includes more than a few components. It's also a good idea to familiarize yourself with the nuances of SPICE so you won't get in trouble with things like convergence, or even worse, misleading results. If anyone has questions about SPICE models and simulating in SPICE, post below and I'll do my best to answer. Happy simulating!

28 comments on “Pick Your SPICE Models Carefully

  1. amrutah
    April 30, 2013

    Scott, Thanks for the post on SPICE models and other model vendors.

           I am a regular user of spice and I have seen that the Hspice models and the BSIM spice models have few of the paraments that are different.  Why is this so?

  2. amrutah
    April 30, 2013

    How do you rate the BSIM4 models which are supposed to track the sub-micron techonlogy and consider the short channel parameters?

      Thanks for the information regarding the CMC.  If I am not wrong, this is the council which will decide the roadmap for the future spice models.

    With the advent of tne SOI and finfet devices the models are evolving a lot, does the CMC decide the models for other technology and devices too?


  3. amrutah
    April 30, 2013

    The EKV models were developed for modelling the device operating near the sub-threshold and deep sub-threshold operation.  With the fast evolution of the BSIM models, Plese correct me if I am wrong, the EKV models are no more used but its good to study these model sets?

  4. Scott Elder
    April 30, 2013

    HSPICE made this departure many years ago.  At the time PSPICE was a very competitive product that cost 10% of HSPICE.  Models were open source, so their motivation, my opinion, would have been to add value to IC design companies whose interest was accuracy first, price second.

    For one example, HSPICE introduced the concept of binning with BSIM models.  This is a process where there are several models for one type of transistor with each model targeting a specific size (or bin).  This was necessary because the BSIM model accuracy at the time was not held over a large range of device sizes.  (i.e. 1um/1um up to 1000um/5um).

    I wonder how much longer this will be important.  Threshold voltage based models are being replaced with physically accurate models so this is less of an issue.

    HSPICE though still solves monte-carlo modeling in a non-standard way.  So who knows. 

  5. Scott Elder
    April 30, 2013

    Yes, the CMC was organized for all types of models.  Here is a cut and paste from their home page:

    “The Compact Model Council was formed in August, 1996, for the purpose of promoting standardization in the use and implementation of Compact models.”

    Re: BSIM4.  Here is a short, thorough comparison.

    Here is a bit of intrigue.  I went to the BSIM homepage and they no longer talk about BSIM5.  They show BSIM4 and then BSIM6.  Not sure what happened.  I suspect the defeat of BSIM by the CMC has caused a lot of rethinking and strategizing to redevelop a leadership position.  If the CMC has any value, it is in provoking these battles.

  6. Scott Elder
    April 30, 2013

    “the EKV models are no more used but its good to study these model sets?”

    Here is a cut and paste from

    “BSIM and EKV groups have agreed to collaborate on the long-term development and support of BSIM6 as a world-class open-source MOSFET SPICE model for the international community for years to come.”

    As I commented a moment ago, the battles continue.  The losers are teaming together to go regain the crown!

  7. Netcrawl
    April 30, 2013

    @Interesting topic, thanks for sharing us this great article. Its really great to see two major groups taking a huge collaboration works- on the long term development and support of BSIM6.

    Building and collaborating for a huge project like this one is very important, it will drive innovation and provide world-class open source tools for the international community. This is exactly what the industry looking for: a new bulk model from BSIM group, which can provide us a source-drain symmetry and accuracy when compared to numerical surface potential solution.  




  8. David Maciel Silva
    April 30, 2013

    Behind boms SPICE simulators exist modules, ensuring that component simulation is close to their operating values ideas.

    For some situations, the bench is still the best option, not only today but as before things have to happen now, so yesterday, we have to use more and more resources for simulation.

    In my experience in designing circuits analpogicos noticed a great evolution starting from MULTISIM to the present day as the PROTEUS, which is a very common tool for all.

    In the specific case of the PROTEUS can import some information to a component according to its operating characteristics.

    This link has some generous information:


    What are the platforms simulation you typically use?

  9. Davidled
    April 30, 2013

    Most models of components are decent in Spice Software package and could be used in the normal operation range of temperature for very beneficial information. But when analyzing the circuit in the worst case, it should be validated in the actual board level, not PC. I might be more looking for interaction model, which is called dynamic model, between one component and other component, if two components are layout in the board. That might provide more realistic simulation of circuits.

  10. SunitaT
    April 30, 2013

    When working with power MOSFETs, it is even better if your vendor has a simulation sub-circuit model that includes package parasitics along with the transistor.

    @Scott, thanks a lot for detailed info on SPICE models. I didnt knew that package parasitics are part of sub-circuit models. If I am not wrong there are different types of packaging, so do we have different parasitics models to mimic those different packaging methods ?

  11. SunitaT
    April 30, 2013

     But when analyzing the circuit in the worst case, it should be validated in the actual board level, not PC

    @DaeJ, If I am not wrong spice models are available for different corners. For example we have different spice models for weak, strong and nominal conditions. Why do you think using such worst case model is not good idea ? 

  12. David Maciel Silva
    April 30, 2013

    I fully agree, but most of the time we can not wait for the time to manufacture a prototype for testing …

    When the options are not the best, do an impromptu, even knowing the outcome ….

    Sometimes the adaptation and testing of the final circuit so different, that when running the first batch nothing works …

    Unfortunately it is a reality …. And then there is possible to discover the source of the problem we have to gather information, environment, temperature, max, min, peak voltage, peak current, and let ai …. A multitude of filters should be made …

  13. Davidled
    May 1, 2013

    By using Monte Carlo worst-case analysis, mainly, circuit may be analyzed with a certain range and limited condition. They give a good baseline for starting point.  If circuit related to high frequency band is analyzed, even bread board provides time delay due to the limitation of board.  In this case actual PCB board is required to analyze the circuit correctly. Instead of changing parameter in the PC, ambient temperature is changed in the chamber.  I think that simulation is very good beneficial for low frequency band circuit typically.


  14. Scott Elder
    May 1, 2013

    @ Maciel

    Platforms….I typically use Cadence if I'm working for someone wealthy….if not, I use Simetrix.  They support HSPICE models (BSIM3v3.2) as well as monte carlo analysis.  

  15. Scott Elder
    May 1, 2013


    “But when analyzing the circuit in the worst case, it should be validated in the actual board level, not PC.”

    I don't agree completely.  For example, are you going to build 1000 boards to test?  Maybe for production, but not to prove your design.  I think building a board is always required obviously, but you can only look at a few parts on a few boards.  With a simulator and corner models from the factory, you can do lots of worst case analysis and what-if studies.

  16. Scott Elder
    May 1, 2013


    “If I am not wrong there are different types of packaging, so do we have different parasitics models to mimic those different packaging methods ?”

    You have to check with the manufacturer and look at the models.  If the model is a subckt and includes inductors, then you most likely have a package model.  You just need to verify that it is the package you intend to use.

  17. Scott Elder
    May 1, 2013


    I don't think this is a matter of looking here OR looking there.  It is that both methods are required to do a solid design.  Both methods have limitations, but both methods also address different issues.

    A good engineer who understands the board effects will do a much better job on a simulator than someone who needs to have a board on a bench to find problems.  Boards are not for finding problems, they are for proving a solution and making small changes for optimization.   

    If you don't prove out the design before you build it, you may be buying and building lots of boards walking through the problems.

  18. Netcrawl
    May 1, 2013

    @Scott you're right a good engineer will definitely work best in design simulator-its the engineer's scratch works, board is “engineer's proving ground” where solution will be test for possible outcome or results. You need to start first at design, simulation's main purpose is to provide us the closest path for building our stuff, guiding us into error free results. 

  19. Davidled
    May 1, 2013

    I did not expect the discrepancy between simulation and PCB board. All I am saying is that simulation is used as base line, and Circuit analysis also tested in the actual board. If you go to board defect, it might be total different subject. Also, as I commented, I highly recommend board level analysis in the high frequency circuit in parallel.  

  20. goafrit2
    May 4, 2013

    >> Plese correct me if I am wrong, the EKV models are no more used but its good to study these model sets?

    That is the diode model or the long channel device model. That remains the basic model for teaching device physics. I think it is still in use. There are many companies that have no business in sub-nm CMOS designs becuase they do not need those small feature sizes. Think of MEMS – that needs EKV model.

  21. amrutah
    May 4, 2013

    Goafrit2: EKV model was developed mainly because the sizes were getting small along with the voltage scaling.  The square law model based models used equations where the transition from linear to strong inversion was abrupt or in other words from weak inversion to strong inversion the model prediction was not accurate which the EKV models were good at by considering the mosfet as a diode.

    “That is the diode model or the long channel device model”   

    I think it was independent of the channel length.  I think Scott mentioned about EKV and BSIM joining the hands for the next level of models.

  22. amrutah
    May 4, 2013

    Goafrit2: “Think of MEMS – that needs EKV model”

       The EKV models are for mosfet, Till now I had never heard of MEMS using the same EKV models. Thanks.

  23. amrutah
    May 4, 2013

    To add,

       A good Analog IC engineer does a god job on simulator when he understands the board layout and the layout on chip, so that he can build all the possible worst case scenarios and corner cases for the design to be solid

  24. amrutah
    May 4, 2013


      Before the chip is fabricated it is always better to check on PC with all the possible worst case corner models (now 4 sigma and 6 sigma models cover most of the fabrication or process characteristics) and WC scenarios of PVT, with board RLC models so that the coverage is good and we have a robust design at hand.  There are much better chances of it to work when validated on actual board.

  25. Netcrawl
    May 6, 2013

    It not just simulator! A good analog engineer with different skills could able to tackle the complexity of today's electronic products, often without the right infrastructure or material

  26. Brad Albing
    May 7, 2013

    Quite right – the good engineer knows (usually from experience) where trouble will occur during the design and manufacturing process and plans accordingly. To extrapolate, the good electronics design engineer even knows where the mechanical engineers will screw things up and therefore have work-arounds in place to deal with those problems.

  27. goafrit2
    May 8, 2013

    >> The EKV models are for mosfet, Till now I had never heard of MEMS using the same EKV models.

    Apparently I would have made it clear that I was talking of MEMS Analog front ends and not the mechanical beams. The transistors used in most of those designs need not be small devices.

  28. goafrit2
    May 8, 2013

    >> A good Analog IC engineer does a god job on simulator when he understands the board layout and the layout on chip,

    Most simulators have nice models for that. I know that Cadence can model all the possible corners in any design. Elite Analog engineers must help layout engineers navigate some of the critical issues that ensure performance is not degraded in fab.

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