While the basic simulation program with integrated circuit emphasis (SPICE) hasn't changed over the past 40 years, the simulation models for metal-oxide-semiconductor field-effect transistors (MOSFETs) have undergone substantial change.
Despite modeling improvements, analog designers who use manufacturer SPICE models for PCB work have not always benefited from these advances. Some consequences of using older simulation models are that the accuracy of simulations will suffer and the ability to even simulate a circuit might not be possible. I thought it might be helpful if I could share some insight into things to watch out for to avoid the headaches.
MOSFET models have traditionally been referred to by their level. For example, originally MOSFET models were called Level 1, Level 2, or Level 3. I am surprised that these outdated model types are still supplied by companies selling discrete power MOSFETs given all the problems they exhibit.
The Level 1 through Level 3 models employ many of the generally accepted current versus voltage (I-V) equations one would see in a textbook. The problem with these models is they don't describe the I-V relationships with one continuous equation and are not always monotonic (i.e., exhibit negative resistance!). This can lead to convergence problems when simulating. To understand why requires understanding a subtle aspect of how a SPICE simulator arrives at solution points in a transient or dc analysis.
Anyone who has studied differential calculus knows that derivatives don't exist at the discontinuity point in an equation. Think of an ideal square wave signal with zero rise time. The slope changes from zero to infinity at the point the voltage starts to rise. This is a discontinuity. While this doesn't happen in a real digital circuit, it does happen when a Level 1, 2, or 3 MOSFET SPICE model is used as SPICE tries to solve the I-V equations on the cusp of going from the linear operation mode — one equation — into the current source mode: a second equation.
If SPICE tries to solve a simulation point around a discontinuity it will fail to converge. The solution will oscillate between both sides of the discontinuity until the iteration variable, ITL1, is exhausted and the simulator stops. This is probably the most aggravating part in simulating circuits using SPICE.
With the advent of BSIM models 1 and 2 from the University of California at Berkeley, non-physical fudge factors were introduced to smooth the IV transition from one region of operation to another. While there were still cases where discontinuities crept in, at least by BSIM 3 the convergence problems were greatly diminished. BSIM 3v3 is still a very popular simulation model because of its good convergence characteristics and accuracy for moderately small geometry devices.
Today, MOSFET SPICE models are more frequently referred to by names like BSIM4, BSIM5, PSP, HiSIM, EPFL-EKV, etc., although many simulators still force those names to a Level number. For example, HSPICE calls their BSIM 3v3 model Level 49. Each of these models addresses the simulation problem from different perspectives.
In 2005, the Compact Models Council (CMC), a working group established in 1996 to decide the fates of all model types, voted out the BSIM model for their recommended future standard. The 65nm and below modeling “hat” was passed over to the PSP model team from Penn State University (now supported by Arizona State University) and the then Philips Semiconductor (now NXP). The vote was a clear majority (written with a smile) of 17 to 14. Actually, it came down more to simulation speed, capacity, and logistics; how the model would be distributed (e.g., Verilog-A code versus C code). Anybody who has tracked SPICE simulation speed claims can just imagine the fight trying to have 31 people agree on a test circuit to prove simulation speed winners.
But 65nm is not something most PCB designers need to worry about for awhile. Rather, if you can work with vendors that supply BSIM models version 3 or later, you will minimize the headaches during simulation. When working with power MOSFETs, it is even better if your vendor has a simulation sub-circuit model that includes package parasitics along with the transistor.
Analog semiconductor companies don't routinely use a simple BSIM-only model for simulating power transistors. Typically their models are elaborate sub-circuits with other modeled components around the device like JFETs to model voltage-dependent drain resistance. More recently they also use tools such as R3D from Silicon Frontline to extract complex 2D and 3D on-resistance and turn-on delay timing. If the models use these extracted features, they are very precise, and more importantly, enable the study of EMI issues related to power FET rise-fall times and Joule heating — extremely important issues when dealing with high-power voltage or current transients.
The ability to simulate a circuit with SPICE before building a board is important if the design includes more than a few components. It's also a good idea to familiarize yourself with the nuances of SPICE so you won't get in trouble with things like convergence, or even worse, misleading results. If anyone has questions about SPICE models and simulating in SPICE, post below and I'll do my best to answer. Happy simulating!