# Power Factor Correction

One of the leading topics in line-operated power-converter design is to take power from the grid but not give any back. In other words, wall plugs should present to the ac source a resistive (and not a reactive) load. A power-factor corrector is the interface between the ac line and power converter that achieves this. So what is power-factor correction and why does it matter?

Why PFC?

A power-factor controller (PFC) is a resistive load to the ac source. It provides a regulated dc output as input to an ordinary converter. Typical power supplies have as input a full-wave bridge rectifier followed by a storage capacitor. While the bridge diodes conduct, the line is driving an electrolytic capacitora nearly reactive load for the line. A reactive load causes line voltage and current to be out of phase, which is sub-optimal for power distribution. Maximum power is delivered when they are in phase. The power factor is the cosine of the phase angle. A resistive load has a phase angle of zero and a PF of one.

Furthermore, instead of dissipating (that is, keeping) power, reactive loads store it and give some back later. This causes waveform distortion and harmonics on the ac line, defiling its purity. Line noise, surges, and dips reduce power quality. The developed world is now at the stage where “electrical environmentalism” is requiring clean treatment of the power line from its users.

What is a PFC?

A PFC appears resistive to its source. This implies that the input current must differ from the sinusoidal source voltage by only a scaling factor. Their waveforms must be identical, though scaled by the effective input resistance of the PFC, by Ohm's Law.

How might we design such a circuit? If a converter such as a boost (common-active) type were controlled so that its average per-cycle inductor current were controlled by a scaled input voltage (n g scaled by Tg ), the resulting current (ig ) would follow the voltage and the converter input would appear resistive. In other words, form a current control loop driven by the input sine wave. Because the loop would require a bipolar range to accommodate a sinusoid, introduce a bridge rectifier at the input. The rectified sine wave (or sine magnitude), n g , is now unipolar (assumed positive going with respect to PFC ground), but is not followed by a storage capacitor. That capacitor is, instead, placed at the output of the current-loop converter. What we have so far can be diagrammed as shown in Figure 1 . Figure 1:  Block diagram of a basic power-factor controller (PFC)

As shown in Figure 1 , our PFC conceptual design provides no control over the dc output voltage. Coincidentally, you can vary the scale factor (or division ratio, if you imagine a voltage divider) for the sine magnitude input controlling the current. If the scale-factor is electronically adjusted by using an analog multiplier, then you can implement a second outer control loop to control the output voltage. Our scheme consequently works like this. The outer voltage loop compares the storage-capacitor output voltage, scaled by a voltage divider, HV , against the controlled voltage, set by a voltage reference. If too low, a voltage-loop error amplifier, AVe , increases its input to the multiplier. The other input is the sine magnitude (voltage-divided first by a fixed divider, Tg ), that is increased in amplitude. The multiplier output now is a larger sine magnitude controlling the current of the current control loop. This loop compares the controlled current to the sensed converter input current.

If the instantaneous value along the sine magnitude input-current is too low, the output of the current-loop error amplifier, ACe , to the pulse-width modulator (PWM) increases, and the PWM duty-ratio, D, increases. This causes the active converter switch to be on longer, increasing the inductor current. This current dumps into the storage capacitor and the output voltage increases. The voltage loop responds accordingly. To summarize, the inner current loop is actually a switching transconductance amplifier with scaled sine magnitude input. It is also a programmable-gain amplifier (PGA), with the gain controlled by a voltage control loop which adjusts average output current io to maintain output voltage n o . The block diagram of the entire PFC is shown in Figure 2 . Figure 2:  Block diagram of the complete power-factor controller

Two blocks (transfer functions), the duty-ratio (or control) to source current Tigd , and the source current ig to output current io or Tigo , represent the converter. Figure 2 also shows the effect of the input voltage, n g , on the converter, in that Tigd is a function of n g . Current- and voltage-loop error (and dynamic compensation) amplifiers have gains of ACe and AVe respectively. Rs is the sense resistor (or equivalent) and He is the current-loop sampling effect. HV is the output voltage divider and Zo is the storage capacitor and loadthe next stage of the power converter. Tc is the transfer function of the closed current loop: The feed-forward path above Tg drives the divider input of the multiplier. As the line voltage varies, the peak-to-average ratio (p /2 is approximately equal to 1.57) remains constant. Consequently, dividing by the average can compensate this variation. The amplitude is thus normalized to a constant value.

Summary

This is a PFC at a functional description level. Design choices that follow include selection of converter type (usually a boost converter), compensation filters AVe and ACe (which are not trivial), and all the details of circuit-level design. What is important to do in design is to have the actual transfer functions of each of the above blocks. Only then is it possible to reasonably model PFC behavior. The derivations of the converter blocks are not trivial but have been worked out in the literature, using Richard Tymerski's switch model
and Ray Ridley's current-loop sampling model.

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