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Power integrity tool caters to scale in digital and analog

One of the biggest challenges for analog designers has been the lack of targeted tools for their needs. There are simply not enough tools addressing analog design, especially on the analysis side. Take power integrity analysis, for instance, the key portion of design flow in which engineers verify power for all modes while evaluating voltage delivered in the implementation of gates and transistors for digital and analog designs, respectively.

Here, while there has been a tremendous effort to address scalability in the digital realm, it’s less so in the analog domain, especially when you look at power integrity in analog designs. Laurie Balch, research director at Pedestal Research, acknowledges that analog designers have traditionally been a far smaller market than digital designers. “However, the proliferation of analog and mixed-signal designs today is making the tools that focus on analog design more critical than ever before,” she added.

Figure 1 Large analog systems are often sent to manufacturing without a detailed analysis of electromigration (EM) and voltage drop (IR). Source: Siemens Software

It’s worth noting that there are good solutions that enable engineers to use SPICE-based analysis for smaller circuits such as amplifiers, drivers, and converters. However, as you get into larger analog systems, where you talk about millions or even billions of transistors, there is no detailed solution that allows designers to get a complete simulation-based analysis for these large systems. The SPICE tools don’t have the capacity.

As a result, design teams have to resort to static analysis, which is a rough approximation, or engineering-centric workarounds where designers have to decide the most sensitive part of the circuit they need to analyze. Then they do that in several scenarios to have confidence in the tapeout of the chip.

That underscores the need for a breakthrough in analog and digital power integrity, the one that takes scalability from digital and applies it to the analog side to offer full-chip dynamic analysis. Siemens Digital Industries Software claims to have this power integrity solution for large chips with digital, analog, and mixed-signal blocks. Its mPower power integrity verification solution offers virtually unlimited scalability for analog, digital, and mixed-signal ICs.

“The mPower tool enables comprehensive power, electromigration (EM), and voltage drop (IR) analysis for even the largest IC,” said Joseph C. Davis, senior director of product management for Calibre Interfaces and mPower Power Integrity at Siemens Digital Industries Software. He added that the current EM/IR sign-off tool suites provide good scalability for digital designs, but not for analog designs.

Figure 2 Lack of detailed EM and IR analysis for large-scale analog circuits puts the whole system at risk. Source: Siemens Software

Pedestal Research’s Balch acknowledges that mPower is specifically focused on helping engineers confirm that their designs operate within the required power envelopes for their end-user applications. “This is particularly vital for chips today that are going into all sorts of mobile and untethered applications for which power utilization and minimization is paramount,” she said. “Since analog and mixed-signal circuitry is often a central component of such devices, being able to simulate the power characteristics ahead of production is key to ensuring design success.”

When it comes to tool support for EM/IR of large analog designs, Siemens’ new power integrity solution has enabled MaxLinear engineers to assess EM/IR during tapeout of large analog circuits with confidence. “The mPower tool allowed us to do something we have never been able to do before,” said Paolo Miliozzi, vice president of SoC Design and Technology at MaxLinear.

Another chip where mPower has been recently used is onsemi’s sensor chip, where half the die is analog and half the die is digital, and it’s married to a pixel array. The existing analog solution has been so difficult to use that the design team preferred hand analysis. Here, mPower provided a single solution for accurate digital power, EM, and IR while covering both analog and digital.

Figure 3 Using a single run for all analysis eliminates extra engineering effort and provides fast turn-around time for full-chip sign-off. Source: Siemens Software

Davis says that mPower is the first scalable solution that addresses both analog and digital EM and IR. So, how does Siemens provide this scalability? More importantly, why is Siemens entering this market right now? “We see trends and changes in the market that create a need that we can address,” Davis said.

He further elaborated that while competitor solutions scale to thousands of CPU cores to run power integrity analysis on large chips, we can do that as well. “What’s different is that we are able to apply that to the analog domain to extend the dynamic analysis to hundreds of millions and billions of transistors,” Davis said. “It was previously limited to a couple of million transistors.”

So, design teams can take that methodology from block level to chip level, allowing engineers to avoid expensive and risky workarounds regarding power analysis for analog circuits. The mPower tool also offers 2x runtime improvements for EM/IR analysis of large analog IP blocks. As Davis puts it, a verification tool must not require more work than the design itself.

Majeed Ahmad, Editor-in-Chief of EDN and Planet Analog, has covered the electronics design industry for more than two decades.

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