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Power-On Reset: The Analog, the Digital & Some of What Can Go Wrong

Many types of electronics can require some kind of power-on reset (POR). Without a proper reset, many things can go wrong. What's worse, with a badly designed reset circuit, things can go wrong with it. Reset is generally required by many types of electronics. Even simple latch circuits made with analog comparators can even require a POR.

Part of the POR is analog and part is digital. The POR sees largest usage in microprocessor, FPGA, and other mixed signal circuits. Some of what is usually included in a reset device includes an under-voltage detection method, a way to assert a valid reset level via driving to a logic low (or sometimes a high) state while in an under-voltage condition, and a time-delay upon valid voltage being reached. Additionally, a logic watchdog input is present on some devices. This monitors a logic output from the microprocessor or FPGA. The watchdog input expects to see low-to-high and high-to-low transitions at regular intervals. If not, a reset is asserted.

With that said, I have seen all manner of things go wrong with reset over the years. Some of the items included the old microprocessor RC delay power-up reset circuits — these often did not include an under-voltage based reset on very early processors. Everything would generally start up fine, unless there was a post power-up sag in the voltage. Then on occasion the logic would become highly illogical in the processor. Furthermore, if the RC delay for the processor (as specified by the processor vendor) was not sufficient for other circuits in the unit to do things like come on frequency, then other parts of the system would “flake-out” even though the processor booted up OK.

These issues lead companies like Dallas-Semiconductor (now part of Maxim), Texas Instruments, Intersil, et al. to come out with one-chip solutions. These were fairly bulletproof, would keep the CPU and other circuits in reset during voltage ramp-up and ramp-down, and would provide for an adjustable reset delay. The reset delay was set by a couple of common methods. One technique used an external RC that set oscillator frequency inside the part to generate time-delay. The other method let the user tie pins high or low to effect the desired delay.

However, with that said, there were often other issues. Some of the ways I've been burned include platinum filaments being included in the packaging compounds. These lead to shorting of the pins. Other issues include larger-sized capacitors subject to breakage in handling. Or — if the mechanical engineers did not nail the vibration analysis of the board and components dead on — subject to shearing off.

Other things that can go wrong include issues keeping battery-backed RAM or even EEPROM in a safe state during voltage ramp. This can often be due to the lower operating voltages for battery-backed flash, and the fact that off-the shelf reset circuits have a brief time of invalid state right on voltage ramp. Another similar issue can be EEPROM depleting the hold-up capacitors prior to write completion, upon loss of power into the unit. This is similar to another reset function that monitors the power-supply input to detect loss just a little bit more quickly. Still, you are at the mercy of the large hold-up capacitors, the value of which has a wide manufacturers tolerance. Further, capacitance varies a lot with temperature.

Jumpers and switches that are intended to disable the watchdog function (used during special testing conditions) can be another source of misery. Vibration, temperature cycling, and human error can cause your carefully designed watchdog circuit to become useless. It's best to use a soldered-in jumper (e.g., a 1206 zero ohm jumper) — something easy to unsolder and re-solder and large enough for a quick visual check.

Modern reset ICs can solve many issues, and I've even seen other issues (not usually associated with POR) solved with one of these in the circuit. It is also possible to perform the reset, and loss-of power functions with comparators and discrete components. One must weigh the pros and cons of each approach — often in compact systems there may not be room to add a larger number of discrete components for a POR function.

What all are each of your experiences with doing the Reset Function for circuits?

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9 comments on “Power-On Reset: The Analog, the Digital & Some of What Can Go Wrong

  1. Dirceu
    July 24, 2013

       There are several non standard applications for integrated POR devices. For example, on a boost converter, connecting the POR output to the gate of a series mosfet its possible shutdown the converter and removing  the undesirable path for dc current flow (input-to-load).

  2. BillWM
    July 24, 2013

    One of the more unusual applications I have seen is to used the POR/WDT to enable a pneumatic back up for an electromechanical / chemical process.  (If the software in anyway hung and failed to toggle lo-hi-lo at the right duty cycle and rate the WDT or the voltage browned out the pneumatic back-up came into play.)

  3. Davidled
    July 24, 2013

    When implementing S/W for safe critical system, system goes to limp-hone mode or safe mode to avoid catastrophic case. Also, Limp-hone mode is thoroughly tested in the bench. Power on Reset or Watch Dog timer is used commonly in SW, even though there is lack of information related to POR/WDT application.  

  4. Netcrawl
    July 24, 2013

    I believe WDT in all new devices has now the ability to generate interrupst instead of resetting the system and since WDT runs from or have its own clock it can used to wake up the devices from sleep modes-this makes WDT an ideal wake up timer. WDT also can easily combined with operation as a system reset source, its main job is automatic handling and recovery. 

     

     

     

     

  5. Vishal Prajapati
    July 25, 2013

    My company is running a Training Institute in which students learns embedded systems. We have covered the basic microcontroller circuits in the practical session. Students make ATmega8 demo boards in their practial. In this circuit we still suggest them to use the old RC Power On Reset circuit along with IC. For the perticular application, this is sufficient for reset as there is only one IC to be sync. There is no external flash or external RAM and it works fine.

  6. JeffL_#2
    July 25, 2013

    I'm having trouble getting a write of user parameters back to data flash on brownout reset on a Microchip part (16F series) but I don't know whether it's an analog or digital problem, I just know that if I put a breakpoint in the brownout portion of the ISR I can never see it execute regardless of brownout voltage setting (and I can access all my other ISR routines without difficulty so it doesn't appear to be a configuration issue). I don't see a lot of help on the data sheet in figuring the size of the holdup cap (and in application there isn't a separate pin for this so you have to calculate total system current drain and your main supply output cap to figure it out) versus the number of bytes to be written (flash write current and worst case timing). It would seem like writing back to flash on the power down cycle to minimize total flash write cycles would be an obvious application situation but they don't appear to give the necessary data or an application note to figure it out so I'm stuck.

  7. Sureena Gupta
    July 25, 2013

    William, I would agree with your thoughts.  System requirements for today's processors, MCUs and FPGA are very complex. Voltage supervisor ICs provide a level of sophistication needed to prevent uncertainty.

    Some supply voltage supervisor ICs offer features like overvoltage (OV) on top of traditional under voltage (UV) monitoring with tight accuracy to protect the design from spikes and transients; watchdog timer / window watchdog timer for system handshake between the processor (or FPGA) and power solution; adjustable reset delay to ensure proper system power-up; and power fail input to help with proper system power-down. 

    I wanted to share a link to an application note from Texas Instrumetns that help explain Window Watchdog Timer functionality and how they can be implemented to add a level of sophistication to your design beyond traditional Watchdog Timer.  In short is helps catch a system error if the processor is stuck n an infinite loop.  http://www.ti.com/lit/an/slva365/slva365.pdf

    Also an application note on How to add additional hysteresis to Voltage supervisor.  http://www.ti.com/lit/an/slva360/slva360.pdf

    I hope it is helpful.

     

    Sureena Gupta

    Engineer at Texas Instruments

     

  8. BillWM
    July 25, 2013

    Sureena, Your post is most appreaciated.   Over Voltage Reset, Crowbar, or Clamping is one area I see many embedded designs go astray in the area of.  Most do not realize that timing on occaision can speed up to much when the CPU, FPGA, Memory or other digital component has a Over Volts Condition.   This can result in logic race conditions, that end in improper operation.

  9. RituGupta
    September 18, 2018

    Don't you wish that there's a power reset button in every day life too? I mean, I would  be very happy if every night it would be as easy as powering down and rebooting to get some of that stress off my shoulders. Sadly, I think that this analogy is only hypothetical – there's way too many things to handle to allow a power down to get in the way…

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