Golden Gate Technology Inc., specializing in nanometer IC power reduction, introduces two new software products — Power Optimize Gold and Power Plan Gold — that work with existing place & route flows from Cadence Design Systems, Synopsys and Magma.
Golden Gate's new power reduction products can reduce total power consumption by up to 25%. Power Optimize Gold reduces leakage and switching power while simultaneously meeting constraints for timing, signal integrity and electromigration. Power Plan Gold creates architectural multi-voltage-island designs by automatically creating complex power grids. This enables sophisticated on-chip power management schemes.
“Power reduction is now our customers' top design concern,” remarked Dennis Heller, Golden Gate CEO. “Our new products integrate with and enhance existing flows, giving chip designers a low risk way to cut total power consumption.”
“We have over 50 successful tapeouts with Power Plan Gold,” said Kelvin Chun, Director of Design Center Application Engineering at Oki Semiconductor.
“From our benchmarks, we determined that, out of all the tools we evaluated, Power Optimize Gold consistently produced exceptional results,” said Dave Holt, CEO, Lightspeed Semiconductor.
Wires account for 5x more power consumption than transistors at the 90 nanometer node, and 30x more power consumption than transistors at 35 nanometers. Since wires burn most of the power on nanometer chips, Golden Gate's power reduction software gives wires the first priority with a patent-pending optimization technology called, WiresFirst. WiresFirst minimizes total capacitance on critical clock and signal nets through route optimization and isolation techniques that reduce power without negatively impacting chip timing, signal integrity, or electromigration.
Power Optimize Gold — Power Reduction at Every Step of the Design Flow
Power Optimize Gold reduces power at many stages in the physical design flow. Power Optimize Gold works with placement and clock tree synthesis to reduce power consumption in the critical clock network. WiresFirst algorithms incrementally rebalance capacitances and restructure logic to recover excess power consumption with minimal perturbation to a design's timing and physical layout characteristics. When used throughout the design process, the various power reduction techniques implemented by Power Optimize Gold are cumulative.
Power Optimize Gold concurrently optimizes across complex libraries containing unlimited process-voltage-temperature (PVT) corners, and supports rich cell libraries that trade off power, timing, and area for the same function. Logic restructuring minimizes switching power without compromising critical chip timing. Cell substitutions with multi-Vth cell libraries reduce leakage current without negatively impacting critical timing. Power Optimize Gold has enough database capacity to reduce power on large designs — up to 10M gates overnight on a 32-bit OS or unlimited gate size on a 64-bit OS.
Power Plan Gold — Increased Productivity & Power Optimization
Power Plan Gold works with silicon-virtual-prototyping tools to automatically create sophisticated multi-voltage-island architectures that supply the optimal amount of current to every device on a chip. With WiresFirst technology, Power Plan Gold gives designers the most accurate power-consumption information, earlier in the design flow than was previously possible. With this data, chip engineers can now build their power supply systems correctly the first time without incurring either costly downstream iterations caused by undersized power grids, or wasted power and silicon resources caused by over-designed power architectures.
Power Plan Gold works with a single data model and integrated power grid synthesis and analysis tools for IR drop, timing and electromigration. This minimizes data translations and simplifies integration with existing design flows.
Power Optimize Gold and Power Plan Gold are shipping now for Solaris and Linux. Power Plan Gold starts at $115,000 and Power Optimized Gold starts at $395,000 for time-based licenses.
Golden Gate Technology, headquartered in San Jose, California, provides leading-edge tools for nanometer IC power reduction that work with existing design flows from major EDA vendors. Using WiresFirst technology, Golden Gate Technology products reduce chip power consumption by up to 25%.
For more information please visit www.ggtcorp.com.
Golden Gate Technology, Inc. is headquartered at 1101 South Winchester Boulevard, Building P, San Jose, CA 95128, Phone: (408) 249-6200, Fax: (408) 249-6240.