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Power Routing in Analog Design

Automating analog design requires that constraints such as symmetry and matching, noise coupling, and the use of shielding be part of the automated flow. Commercial routers capable at the device level can handle some of these types of constraints, but handling power net routing is typically done by planning manually.

In the digital world, power distribution methodology is much easier. With row-based, standard cell placement and routing (P&R), and the availability of relatively many metal layers, power rings and meshes can be easily generated automatically. True, this can become more complicated as designers seek to use less power by using power switches and have multiple voltage domains, but there are well established EDA tools to help designers analyze and optimize power distribution schemes.

For small analog IP blocks, power routing can often be relatively simple. A common approach is to start with a “template” cell defining the desired block size, pin positions, and VDD/VSS rails, typically at the top and bottom of the block. However, even for relatively simple blocks, the power hookup to devices has generally been done manually. Actually, there is no reason why a mesh-type structure can’t be used; for example, two layers are shown in Figure 1, which shows VDD/VSS rails at the top and bottom of the block with an irregular H-shaped mesh in the center. The key to achieving this is the ability to place and route devices, signal nets, and power nets simultaneously. Device S/D pins can directly strap to the power mesh to give a clean routing style.

Figure 1

Automated power routing mesh for an analog block

Automated power routing mesh for an analog block

Widths of power tracks need to be considered carefully for analog layout. As geometries get smaller, tapering of power nets may be required since uniform-width nets may be too wide for individual transistor tap-offs, but too narrow due to electromigration rules for higher current portions of the nets. In this case, careful consideration of current flow is required in order to size the net segments appropriately. (For more details visit “Current-driven wire planning for electromigration avoidance in analog circuits.”) Simulation results of transistor pin currents are required here in order to accurately model the current requirements of the power nets (and potentially the signal nets, too).

Another common approach is to use combined power and guard rings/rails. The “variable mesh” approach can also be used here, although it becomes more complex as guard rings require single layer (i.e., wrong way) preferred directions. Again, device S/D pins can tap into guard rings to simplify local power routing.

A further development would be to support hierarchical power routing, where power pins on the lower-level blocks strap into the higher-level cells’ mesh. Once again, actual net widths need to be computed accurately for this approach.

As can be seen, automated analog routing presents challenges compared to digital power distribution. However, with new techniques and methodologies, automation is possible, and the goal of speedier design iterations can be achieved, enhancing productivity.

7 comments on “Power Routing in Analog Design

  1. goafrit2
    September 6, 2014

    As can be seen, automated analog routing presents challenges compared to digital power distribution. 

    I never like the constructs of automated analog routing because nothing in analog should be automated. It never works optimally. However, should you do it, first get all the critical signals manually routed. The non-critical ones can be auto-routed. Even with that, you may be out of luck during testing time.

  2. goafrit2
    September 6, 2014

    >> Another common approach is to use combined power and guard rings/rails. 

    Guard rings are good but they take away area which could have been another chip especialy when making ultra-cheap consumer products. You have a budget to make a chip for $0.50. Guard rings become luxuries. Cost should drive everything that happens inside a chip.

  3. Keith Sabine
    September 7, 2014

    Guard rings may not always be necessary, but they are not luxuries. They can usefully reduce substrate noise coupling – I have seen a chip fail due to this; the solution was to properly guard ring the PLL in the design and position it away from the noise source. It cost area, but it worked.

  4. Keith Sabine
    September 7, 2014

    “I never like the constructs of automated analog routing because nothing in analog should be automated. It never works optimally.”

    I agree that not everything can be automated. But there is definitely a place for automation in non-super-critical blocks where you can get a result in minutes, not days. And then simulate and find yes, you need to tweak your design.

    A good analog layout engineer will be thinking of the placement of devices and how to route them, with all the constraints, simultaneously. Most current tools don't work that way – they look at placement and routing as seperate problems. They need a lot of guidance to get even a vaguely useful result. Only by considering the placement and routing as a single problem can automation really help.

     

  5. fasmicro
    September 9, 2014

    You are correct. Yet when the cost of failure is marginal to the propensity to lost sales, it makes no sense. If you have a toy that needs to sell for $4 and you think you must make  a chip that does not fail, there is a business risk there. Managing that is part of the business. But the best strategy  is not about best quality. There is a mix in that. You can have quality no one can afford and that means you are out of business. Concorde was discontinued because the quality took it out of the range of air travelers.

  6. fasmicro
    September 9, 2014

    >> Only by considering the placement and routing as a single problem can automation really help.

    Placement unfortunately cannot be automated either since the CAD does not understand the importance of that block. Automation is for the business of digital, in analog, the value is not that great.

  7. goafrit2
    September 9, 2014

    Layout is one of those jobs that never help you grow in your career. Management does not even see you as being important. It is a very stupid job to be a layout engineer. Earn the dollars but that is not a career in the industry. I am not sure there is one that can lead any multi-displinary team. The best career path remains DESIGNER.

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