In my previous blog, New Management Moves Silvaco in New Direction, David Halliday, CEO, made an interesting comment. He said, “Whereas many digital designers are concerned about power consumption, the analog market is more concerned about the quality of the power.”
When we are performing a system-level simulation, including the analog components, how does power get handled? This is an interesting question because the analog and digital worlds are very different in this respect. The desire to reduce power in the digital domain has led to techniques such a power gating, where the power supply is turned off from a portion of the design when it is not actively being used.
Another technique is varying the supply voltage, which in turn affects the performance of the design and usually requires a modification of the operating frequency to compensate for the slower operation. Now here is where it gets interesting. The whole notion of the power supply is foreign to a digital simulator. Gates are just magically connected to the supply and ground rails, and the only things that are modeled are the signal paths. Because of this powerful omission (pun intended), what happens to the supply rails is being captured in a separate file.
This is called “design power intent,” and two standards exist today: CPF (common power format) and UPF (unified power format). The good news is that these two standards are in the process of merging, although it will take time because of some fundamentally different approaches that they take.
So what about analog? Well, the power rails are explicit in the schematic, and no analog simulator could operate without knowing their voltage levels. But if we were to start applying power gating or variable voltage to analog blocks, then we would have to stop treating them as perfect power sources, or even fixed voltages. They too would have to become signals that need to be solved along with everything else. Designs have migrated beyond the approach taken in the past where the analog domain was always powered on, and the digital logic that it interfaced was fed from the same supply.
This does create a couple of small dilemmas, because in one domain power intent is indirectly specified, and in the other it is an explicit part of the design, and these two pieces have to be brought together when doing mixed-signal power-aware verification. This is even more important if an analog circuit is being used to feed the digital logic, as might be the case with power regulators.
Analog tools are becoming able to output power information in a CPF format, but more work is necessary in this area because much of the digital implementation flow is driven from these files, such as synthesis, place, and route, etc. Without having all of the information it might become difficult to perform all of the possible optimization.
The second important piece of the puzzle is the connect modules that are used to interface between the two domains. These have to be upgraded so that they are voltage aware, know how to deal with isolation, and how to deal with cells where state retention is necessary.
Some of the complexity can be seen if we consider the small design snippet below where there are three power domains and two voltages being used, which adds an extra level of complexity for the analog design as well.
In this case it might also be possible to have the analog work from a single voltage and then to do level shifting in the connect modules, but that might also create a new set of problems.
Have you seen cases yet where the analog blocks need to deal with variable voltage or be in a separate power domain from the digital circuitry? What other problems did it create?