Powerful Compromises

In my previous blog, New Management Moves Silvaco in New Direction, David Halliday, CEO, made an interesting comment. He said, “Whereas many digital designers are concerned about power consumption, the analog market is more concerned about the quality of the power.”

When we are performing a system-level simulation, including the analog components, how does power get handled? This is an interesting question because the analog and digital worlds are very different in this respect. The desire to reduce power in the digital domain has led to techniques such a power gating, where the power supply is turned off from a portion of the design when it is not actively being used.

Another technique is varying the supply voltage, which in turn affects the performance of the design and usually requires a modification of the operating frequency to compensate for the slower operation. Now here is where it gets interesting. The whole notion of the power supply is foreign to a digital simulator. Gates are just magically connected to the supply and ground rails, and the only things that are modeled are the signal paths. Because of this powerful omission (pun intended), what happens to the supply rails is being captured in a separate file.

This is called “design power intent,” and two standards exist today: CPF (common power format) and UPF (unified power format). The good news is that these two standards are in the process of merging, although it will take time because of some fundamentally different approaches that they take.

So what about analog? Well, the power rails are explicit in the schematic, and no analog simulator could operate without knowing their voltage levels. But if we were to start applying power gating or variable voltage to analog blocks, then we would have to stop treating them as perfect power sources, or even fixed voltages. They too would have to become signals that need to be solved along with everything else. Designs have migrated beyond the approach taken in the past where the analog domain was always powered on, and the digital logic that it interfaced was fed from the same supply.

This does create a couple of small dilemmas, because in one domain power intent is indirectly specified, and in the other it is an explicit part of the design, and these two pieces have to be brought together when doing mixed-signal power-aware verification. This is even more important if an analog circuit is being used to feed the digital logic, as might be the case with power regulators.

Analog tools are becoming able to output power information in a CPF format, but more work is necessary in this area because much of the digital implementation flow is driven from these files, such as synthesis, place, and route, etc. Without having all of the information it might become difficult to perform all of the possible optimization.

The second important piece of the puzzle is the connect modules that are used to interface between the two domains. These have to be upgraded so that they are voltage aware, know how to deal with isolation, and how to deal with cells where state retention is necessary.

Some of the complexity can be seen if we consider the small design snippet below where there are three power domains and two voltages being used, which adds an extra level of complexity for the analog design as well.

In this case it might also be possible to have the analog work from a single voltage and then to do level shifting in the connect modules, but that might also create a new set of problems.

Have you seen cases yet where the analog blocks need to deal with variable voltage or be in a separate power domain from the digital circuitry? What other problems did it create?

Related posts:

7 comments on “Powerful Compromises

  1. RichQ
    August 27, 2013

    Digital guy here: I'm not even an analog novice, but it seems to me that having a variable analog supply in order to save energy would be a disaster. Or are analog designs linear in their response to rail voltage? It seems to me that bias levels and reference voltages wouldn't scale linearly with shifting rail voltages, and that would in turn affect things like gain and stability as well as the output signal. The design problem to characterize the analog circuit's operation in such a variable condition seems like it would become horrendously complicated, if it could be done at all. And it seems like the power savings would be small anyway.

    Am I wrong?

  2. samicksha
    August 27, 2013

    i am still not sure but yes UPF+ CPF makes good sense, saving power is a primary goal 2day, and designers are forced to use sophisticated techniques such as clock gating, multi-voltage logic, and turning off the power entirely to inactive blocks i.e.  file format for specifying power-saving techniques early in the design process…although i am still on way checking milestone before we reach our destination.

  3. Scott Elder
    August 27, 2013


    Many older analog products work from say 2.5V to 40V.  I'm thinking about amplifiers and voltage regulators for example.  But that is for a steady application of the power supply.  Things would fall apart very quickly if the supply was constantly jumping around.  Especially in audio applications.

    PSRR (Power Supply Rejection Ratio) is a analog specification that conveys a analog parts susceptibility to supply voltage changes.  Not unreasonable to see 60dB or more (i.e. 1 part in 1000 relative change, 5mV change for 5V supply change)

  4. RedDerek
    August 27, 2013

    Closely related is the Cholesteric LCD display technology. This uses 5V logic that is driving clocks and counters to develop different output voltages per output pin (up to 32 on one IC) to control the column voltages so that a grey scale of a particular color can be generated. Then mulitply this by three (red, green, blue) and then with as many columns for the display. The digital realm cannot match this type of application.

    By the way, a Cholesteric LCD is an ultra-low power display in that it only requires power to change the image. Once the image is generated, the power supply can be removed and the image will remain indefinitely. Look up Kent Displays for more information. (No relation to them.)

  5. samicksha
    August 28, 2013

    The pitch varies with temperature and it can also be affected by the boundary conditions when the chiral liquid crystal is sandwiched between two substrate planes.

  6. Aloali
    September 19, 2013

    Brian, you mentioned, “Analog tools are becoming able to output power information in a CPF format”.  Could you identify some of these tools please?

  7. BrianBailey
    September 19, 2013

    I prefer not getting into details about vendor tools because if I say one tool does it and dont know that the others do it, then they get upset. I am aware of at least two tools from major vendors that are doing this, so I wouold suggest that you ask the vendor of the tools you currently use. If they dont have it, tell them that you would find it useful. This is the only way that they learn as to what features they need to add.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.