Recently I was looking at different reference designs and resources available to power an FPGA. I found one design that was created for ease of use, utilizing integrated inductor modules, one that was cost effective since it used discrete components, and another design that was made with PMBus devices, giving an engineer utmost flexibility to control and monitor each rail. Despite the variation in all these designs, one commonality is that the power management solution takes up a decent chunk of board space with regulators, LDOs, reset ICs, sequencers, power stage, and so on.
Today, I will discuss a challenge faced by every engineer when powering your FPGAs: The ever increasing power solution footprint size as the number of loads increases.
There are several innovative and creative ways to reduce the power solution footprint, however, now I will concentrate on the power of integration — i.e., multi output regulators with integrated features. Another tactical way of reducing footprint is using load switches where possible to minimize cost and size. (For more information on the load switch solution, see this Power House blog.)
When powering a solution that includes an FPGA, you need a number of output voltage rails with different loads. Quite a few of these rails need to power up and down sequentially (sequenced) according to system requirements and the FPGA needs. One easy way to reduce board space for this power solution is using highly integrated devices like power management integrated circuits (PMICs).
PMICs vary in their level of sophistication, from multi-output regulators (dual, triple, and so on) to integration of features such as power good, enable, soft start, voltage supervision, LDOs, OCP, OVP, and so on. An effective cascade of integrated enables and power good pins can be implemented to achieve the sequence similar to the one shown in the figure below without the need for an external sequencer. Although, if high sophistication is required, an external sequencer is recommended.
(For a larger version, click here.)
Although a PMIC is great for powering an FPGA in space constrained applications, one drawback of using a PMIC is that you have a centralized PMIC with traces running to each load, which can pick up noise and jitter. This drawback can be minimized by following the layout considerations provided in this application note, effective use of noise filtering circuitry, or appropriate usage of low-noise/high-PSRR LDOs.
Considerations when selecting a PMIC to power an FPGA
First: Input/output voltage rating and load current of each rail in the PMIC.
Second: Switching frequency and the switching regulator topology since this can impact the ripple noise on the DC rail, which in turn can impact the operation of the FPGA. (In case you have more questions on this subject, please leave your feedback in the comments below, and I can address them in my upcoming blogs.)
Other considerations: Thermal performance of the PMIC package along with the level of sophistication of this PMIC. The level of sophistication of the PMIC can help eliminate the need for external components like reset IC, sequencer, LDOs, and so on.
An ideal PMIC for an FPGA will vary with each engineer’s design, based on power requirements. This link is a good starting point to review different PMICs that are available to help reduce the footprint of your power solution.
Please share your experience if you have successfully reduced the footprint size of your power solution for FPGAs using a PMIC.
Related posts:
- Silicon Carbide FETs Shine in SMPS Applications
- LDO, Switching Regulators Get Some Deserved ‘Fundamentals’ Attention
- Digital Power Supplies Are Getting Easier
- Active Load for Power Supply Testing
- Powerful Compromises
- Power-On Reset: The Analog, the Digital & Some of What Can Go Wrong
- PMBus – What the Heck Is It?
- Reverse Recovery Time Significant in High-Power Supplies
I wonder if total of number of cell size might be optimized in the same foot print by using optimal shift register. So, I think that Power consumption of chip would be depending on the total number of cell size inside chip.
I read about Zynq-7000 that fused features of an ARM high-end microcontroller with FPGA fabric to make FPGA easier for embedded designers, any more info on same.
http://www.programmableplanet.com has information on the Zynq that will move to Programmable Logic Design Line on EETImes in the comming days.
>> So, I think that Power consumption of chip would be depending on the total number of cell size inside chip.
The key factors that determine power consumption is capacitance, voltage and the frequency (0.5CfV^2). So, if you increase the cell size while keeping the total capacitance low (the parasitics), you can still be fine with power. The frequency does not scale with chip size, it is simply the clocking speed.
I would look at the power down mode that FPGA consume near-zero power. This mode is controlled by the dedicated pin. Then, this mode latches all logic arrays. The present gate would be a frozen state.
If we account on FPGA power consumption can only accounted on function it is performing and the frequency it is operating at.
@DaeJ – Not completely sure if you meant that you would use a shift register to sequencially enable multiple power supplies. But if you did, note that you could do the sequencing with a shift register, but it would not give you as much flexibility as a device designed specifically to do power supply sequencing like the UCD90120A.
My intention is to get zero amps instead of a few hundred micro amps for parasitic current. To achieve this goal, I think that each D flip-flop register with other register would be completed sleep mode by using bit controller of each cell.
@DaeJ – OK – you're looking at super-low power applications. Understood.
When operating a solution that contains an FPGA, you require a number of output voltage rails with dissimilar loads. Quite a few of those rails need to control up and down successively according to system necessities and FPGA needs.
>> This mode is controlled by the dedicated pin. Then, this mode latches all logic arrays.
That takes care of your dynamic power but has not solved the problem of your static power dissipation. Nevertheless, great idea but will be challenging for a more complex circuit