Programmable clock generator minimises component count

Providing a programmable clock that serves as both source and system clock, Analog Devices'AD9520/2 multi-output clock generators boast a 512byte embedded memory block that enables easy configuration.

By programming a specific set of output conditions via the on-chip memory, designers can configure the AD9520/2 as the source clock to ensure initial processing functions are synchronized when the system is powered on or reset, thus minimising system start-up programming requirements. Alternative clock ics, according to ADI, would require a separate source clock that must be independently matched to the system processor or microcontroller in order to program the system clock chip.

In addition to the on-chip EEPROM and phase-locked loop (PLL), the AD9520/2 integrates dividers, fanout buffers, and a voltage-controlled oscillator (VCO) that tunes from 1.4GHz to 2.95GHz. An external 3.3V/5V VCO/VCXO (voltage-controlled crystal oscillator) of up to 2.4GHz also can be used. The PLL/VCO clock-generation circuitry has a phase noise of -150dBc/Hz at a 10 kHz offset on a 200-MHz clock signal, while the clock distribution fanout channels boast jitter performance of 225 femtoseconds.

For applications requiring redundant references, two reference inputs provide switchover, while a PLL holdover mode maintains the output frequency in the event of a lost reference signal. Zero delay operation is available to ensure phase alignment between inputs and outputs.

The AD9520 offers 12 differential low-voltage positive emitter-coupled logic (LVPECL) outputs in four groups, each with a 1 to 32 divider and phase delay. The AD9522 has 12 differential low-voltage differential signalling (LVDS) outputs. Alternatively, the devices offer up to 24 single-ended CMOS output configurations up to 250MHz.

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