Hillsboro, OR — Lattice Semiconductor Corporation introduced its revolutionary new family of ispClock in-system programmable clock generator devices. The first devices in the ispClock5500 family, the 10-output ispClock5510 and 20-output ispClock5520, combine a high- performance clock generator with a flexible, Universal Fan-out Buffer. The on-chip clock generator can provide up to 5 clock frequencies ranging from 10MHz to 320MHz using a high-performance PLL and clock multiply and divide facilities. The Universal Fan-out Buffer can drive up to 20 clock nets using either single-ended or differential signaling, with individual output control for improved signal and timing integrity. The new devices provide an unprecedented level of performance and flexibility in support of high-performance clock network designs on electronic circuit boards. The new product family marks the first application of Lattice's programmable mixed signal technology to the clock integrated circuit market, estimated at $1 billion and projected to grow at a 20% annual rate over the next four years.
First Single-Chip Solution for Entire Clock Tree Design
Within the devices, seven 5-bit counters (input, feedback, and five output) provide fine granularity in output frequency selection. The high-performance Universal Fan-out Buffer has a maximum pin-to-pin skew of 50ps regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70ps. The output skew of each clock net can be further controlled in delay increments of 200ps (lead or lag) to compensate for differences in circuit board clock network trace length. In addition, both the reference input and the Universal Fan-out Buffers can support a wide variety of popular single-ended and differential logic standards (LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL) at a variety of voltage levels. The input termination and output impedance of each output can be individually tuned to match each trace impedance, resulting in clock nets with high signal integrity.
“Lattice is extending the benefits of integration, in-system programmability and superior performance to clock management,” said Stan Kopec, vice president of corporate marketing for Lattice Semiconductor. “Historically, clock networks were designed using multiple devices with limited functionality at various levels of the clock hierarchy. The new ispClock devices are the first products that conveniently and accurately solve the entire clock tree design problem with a single chip.”
A Comprehensive Improvement Over Traditional Clock Network Design
Clock networks are traditionally designed using simple components such as fan-out buffers, clock generators, delay lines, zero delay buffers and frequency synthesizers. Timing errors due to unequal PCB trace lengths are addressed by using trace length matching through serpentine trace layouts. Trace impedance mismatch is frequently mitigated by trial and error selection of series resistors.
In contrast, ispClock5500 devices compensate for timing errors due to different trace length clock nets through a programmable skew feature, match trace impedances with output impedances by programming each output characteristic, and reduce EMI by programming output switching speed or slew rate. This results in board space savings, improved signal integrity, a simpler clock net hierarchy, improved timing convergence and lower cost.
The ispClock5500 devices' ability to store up to four timing and output configurations and easily switch between them further extends their utility by supporting easy clock margining (operating a circuit board at higher than typical frequency to evaluate design robustness) and power management (conserving dynamic power consumption by “downshifting” to a more efficient, lower frequency when performance is less critical). In-system programmability via the on-chip boundary scan port helps debug complex timing problems and tune individual network timing for best performance.
PAC-Designer Version 3.0, Lattice's PC-based mixed signal design tool, provides simple and intuitive pull-down menus for configuring all programmable features of the ispClock5500 devices. In addition, utilities such as a Skew Editor, Frequency Calculator and Frequency Synthesis support easy configuration of various counters while operating the PLL in its optimal operating range. Design configurations can be downloaded quickly into ispClock5500 devices via the PC parallel port. This version of the software can be downloaded for free from www.latticesemi.com
Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGA), Field Programmable System Chips (FPSC) and high-performance ISP Programmable Logic Devices (PLD), including Complex Programmable Logic Devices (CPLD), Programmable Analog Chips (PAC), and Programmable Digital Interconnect (GDX). Lattice also offers industry leading SERDES products. Lattice is “Bringing the Best Together” with comprehensive solutions for today's system designs, delivering innovative programmable silicon products that embody leading-edge system expertise.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037.
Designers of circuit boards have to deal with several clocks when laying out a board. Among them are the main CPU, memory, ASIC chips, complex programmable logic devices (CPLD), and the power supply. Lattice noticed that engineers were still using discrete components to build their clocks, thus adding significantly to the component count. Lattice took the essential components of the clock network, clock generator, sources of the frequency and the fan out buffer, and put it all together on one chip and made it programmable — and that essentially is the ispClock.
In the clock chip marketplace speed is king and if you want to increase your system speed then you increase your clock speed. Designers also increase the speed of the clock when there is a need for improved signal integrity or reduce errors between two chips. Also, as the frequency increases the timing available for the setup and hold times causing trace length mismatch to become a significant issue. Clock mismatch and output to output skew are other issues for designers. These are difficulties that can make every designer's job a nightmare, and that's where Lattice stepped in. The company decided it could resolve these issues with one comprehensive design — one chip for all clocks.
How it works
The ispClock 5500 programmable clock has a universal fan-out buffer. It generates multiple clock frequencies that are very accurate. The key performance blocks of this chip are the high-performance PLL for clock generation, programmable on-chip dividers and programmable loop filters — and that means you don't have to add RC networks. Lattice calls this a universal standard buffer because it interfaces with most common logic input standards. Additionally, every output has its own slew control for operations like EMI reduction. Outputs can be skewed relative to the other outputs. A skew manager helps you control the output skew. It also has on-chip termination that is programmable to make the clock output impedance comparable to the trace it is driving.
You may wonder if the chip can drive more than one fan out buffer at the same time to drive the likes of LVDS and SSTL. It can, and you could use it for the same frequency on the same PCB. This helps solve network problems by mixing and matching the output voltages and standards, which provides the best signal integration by fine tuning the output impedance.
The 5500 is chock-full of functions. The input can be configured through software as LVTTL, LVCMOS, SSTL, HSTL, LVDS, and PVPECL. You can also program the input termination resistors with the software. Additionally, the device has a PLL on chip, contains input dividers, a phase and frequency detector, a filter, and a VCO. The 5500 also contains 5 clock output dividers and an output routing matrix to connect to any output, universal fan-out buffer with a skew control for each output and the output drivers. Finally, every output buffer can be individually configured to what you need.
Its capabilities are also significant. The reference clock can be selected from 10 to 320 MHz (the input clock range). The operating frequency of the PLL core ranges from 320 to 640 MHz. Five output clock frequencies can be generated, you can direct any frequency to any output in the output routing matrix, and the universal fan-out buffer drives up to 20 outputs organized in 10 banks with different voltages. For example, you could have +2V driving LVCMOS 2.5V and the next two driving LVCMOS 1.8V and the next set could be LVDS at its own frequency. So it means you could have single-ended or differential signaling. You can mix and match output standards. If you use single-ended signaling like LVCMOS you could set the resistor value from 40 to 70 ohms in 5-ohm increments.
The frequency of the PLL is the basis for generating the skew steps, which is a good reason for choosing the maximum PLL frequency of 640 MHz. The skew step is approximately 195 ps. Since light on a PCB travels about 1 inch every 200 ps depending on the PCB material, Lattice determined that to compensate for the mismatch they needed to offer a PLL frequency of 640 MHz with a skew step size of 195 ps. This is a big deal because many designers struggle with the trace length management and Lattice offers software that helps get the trace length matching down as small as one inch. The output skew has independent programmable skew on a per output basis. This simplifies the trace-length matching. If you have to fine-tune the set-up and hold times, the software lets you select a different skew value to compensate for different chips.
An evaluation board is available (PAC systemCLK5520) for evaluating with your chips. Lattice also offers free downloading of its PAC-Designer software. The PAC system includes the designer software the ispPAC evaluation board and a download cable.
This is a significant introduction for Lattice because designers will see the advantage gained by having one chip to control all their clocking functions and replace synthesizers, generators, and clock fan out buffers. That's a good trade.
Prices for the ispClock5520 device start at $18.25 in 1000 piece quantities. The device in a 100-pin TQFP package is available immediately in both commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature grades. PACsystemCLK5520 evaluation kits are also available through authorized Lattice distributors or on the Lattice Web site for $295.
You can get more information about ispClock from the ispClock5500 family data sheet but you will have to first create a Lattice web account.