Puzzling Opto Circuit

Ray Koosha, EE at SAFT America, Inc. and one of our Analog Aficionados community members, sent us this circuit he found on the internet with the following comments:

Apparently, when there is a “high” at the input, photo-transistor turns on causing Q1, Q2 and eventually Q3 to turn on, bringing 24V at output to Vce of Q3 and if Q3 goes into saturation, output is shorted.

I am confused as what the circuit wants to do.

Please send us your assessment of this circuit.

14 comments on “Puzzling Opto Circuit

  1. micd22
    June 10, 2015

    Add a resistor between your opto collector and 24V rail.  Maybe a resistor between Q3 collector and the 24V rail as well unless you are intentionally trying to short out your 24V supply when Q3 is on.

  2. rosekgiz
    June 10, 2015

    It appears that this circuit is being used to rapidly discharge filter capacitors – given that the 3055 is a beast of a transistor.  Evidently, the parallel R/C network is there to provide a bit of delay, perhaps?

  3. paullMK8
    June 10, 2015

    Looks like a smoke generator to me. Even if Q3 did not short the 24V rail, Q1 would short it through Q2 base emitter, Arrowed R and C actually make sense as the uncommitted base connection on a CNY17 is usefully  tied to emitter with high value R for noise immunity.

  4. EB2
    June 10, 2015

    Is this a solid state relay? The 24V being the output rating, not supplied bus voltage. Like an Opto22 or Crydom device.

  5. EB2
    June 10, 2015

    And for those no familiar with optocoupler/optoisolator circuits, the 4.7k parallel resistor at the input reduces the linear operating range, raising the input voltage point when the output transistor comes out of cutoff and begins conducting. At low voltage, virtually all of the current goes through the 4.7k, rather than the indicator LED and optocoupler LED.

  6. roynza
    June 10, 2015

    It must be assumed that “24V” is not the raw output from a PSU but connects to a load, powered by 24Vdc. This is a typical open collector connection. The opto-isolator has a resistor across its base/emitter – this reduces the gain of the transistor, but would also discharge the capacitor later. Once adequate bias occurs at the optocoupler, the capacitor is charged and the 3055 switches on, and effectively kills it own supply. The capacitor discharges via its resistor (time constant RC) and the process repeats itself. Basically a load connected to 24Vdc is continuously switched on/off at RC time constant when enabled by adequate bias at the optocoupler input.

  7. j.sinnett
    June 10, 2015

    I'm leaning more toward the theory that this is a DC Solid-State Relay, and the 24V is not a power supply rail but rather the output of the SSR.  Any load could be connected between the actual 24V supply and the collector of Q3.  As long as the input optical circuit is active, then the output voltage at the collector of Q3 will be “low” – meaning one VCEsat (Q1) plus VBE (Q2).  Both of those transistors have to be biased on to deliver base current to Q3.


    As for the resistor and capacitor shown connected Base-Emitter on the phototransistor, maybe the person who drew the circuit is simply thinking of the simple transistor model, where these components are part of the physics of the transistor.  In other words, maybe the phototransistor is the limiting factor for bandwidth (switching frequency) of the circuit.  Although the venerable 3055 is not exactly a high-frequency device; it can barely handle the full audio spectrum, if I recall correctly.

  8. samhead
    June 10, 2015

    Yup, a classic 3A 60V SSR

    Cap is for the Showering arc test compliance. page 94.


  9. studleylee
    June 10, 2015

    If think the goal was to have a logic-like input level cause the opto-coupled beefy MJE3055 to drive a load to ground. It basically now uses whatever placed on the “24Vout +” net to bias the transistors and then pull, using the MJE3055, to the  “24Vout -” net.

    The load would need to be resistive to limit the CtoE current passed through Q2 into the base of Q3. I would have put a current limiting base resistor into Q3. Q2 is also not base R limited.

    Q3's hfe is not too great so Q1 and Q2 raise the gain in 2 stages.

    Overall now it is an “optically controlled crowbar” that might get hot or oscillate since the biasing is dependent on the load( “24Vout +” net to bias ) so Q3  will be in a not fully saturated state.

    Dang, I'll have to simulate it in LTSpice now you got me interested.

    If this was drawn from a simulation attempt, the RC on the opto BE may be an attempt to model or effect the the risetime/falltime character of this opto.

    -Lee Studley





  10. studleylee
    June 10, 2015

    @SamHead  Thanks I should have read your post prior. Nice appnote for ref. -Lee

  11. studleylee
    June 10, 2015

    @ SamHead:   Nearly identical to figure 4.3 ( p31appnote/p40 of PDF )


  12. Steve Taranovich
    June 10, 2015

    @samhead—nice catch!

  13. David Ashton
    June 10, 2015

    As Samhead points out, the RC on the optocoupler is for RFI protection.  But the biggest puzzle is that when Q3 is saturated it will only have around a volt on it which is not a lot for the rest of the circuit to work on.  This would be greater at large Q3 currents – Onsemi's data sheet says up to 8V if it's passing 10A – but you better heatsink it, that's 80W gone!  A better idea whould be to put your load in either the emitter or collector line of Q3, but then you lose your 2-terminal output.  I'd guess the truth is somewhere in between – a Q3 VCEsat of a few volts…??  It would only really saturate at large output currents where VCEsat  will give the rest of the circuit enough to work on?

  14. Steve Taranovich
    June 10, 2015

    @David Ashton—Excellent in-depth analysis and design advice David—thanks

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