 # PWM DAC Design

The question that arises in the design of a simple PWM DAC is what the low-pass filter pole frequency should be relative to the PWM frequency. This question is addressed by deriving the design equation.

Microcontrollers typically have PWM outputs that can be used as D/A converters when speed is not a constraining design criterion. A simple RC integrator following the output from the μC averages the PWM, where the average voltage is and D is the duty ratio (or duty cycle) of the PWM output; V is the high-level and full-scale (fs) voltage. For lightly loaded CMOS outputs, it is the supply voltage, VCC . The PWM square-wave from the μC and the RC-integrated waveforms are sketched below with exaggerated ripple. The voltage ripple is And the full-scale fractional ripple is For n bits of resolution, the fractional ripple (as a fraction of fs) is required to be The exponential vH and vL waveforms follow from basic circuit analysis. The vL (t) waveform during the off-time begins at the peak ripple voltage of vH and exponentially decays toward 0 V, the logic low-level voltage of the PWM output. The time of the minimum vL value is at t = (1 – D)•Ts . Substituting this value for t , the value of vL is And for vH , the rising exponential begins initially at vL and rises over a voltage range of VvL toward a target voltage of V . The value of vH is that at t = D•Ts : Substituting vL into the expression for vH and simplifying, Then For Ts << 1, in general, using the first two terms of the Taylor-series expansion of the exp function, Then the fs fractional ripple and its approximation are For D = 0 and 1, the ripple is zero and is greatest at D = 0.5. Then A more convenient ratio than that of time is that of frequency for RC integrator design. The RC integrator pole or break frequency is its bandwidth; ωbw = 1/τ and Also, Combining these and solving for the ratio, For n -bit resolution, substitute Δv/V = 2n . The result is If solved for the number of bits required, the design formula becomes From this design formula, for which τ = R•C = 1/2•π•fbw and fs is the PWM frequency, the following table gives the calculated values for an even number of bits of resolution. The numerical pattern is simply that fs /fbw changes by an octave for every bit of change in n. A mnemonic for remembering the formula is that, for 6 bits, the PWM frequency must be 100 times higher than the integrator pole frequency. Then scale by 2 for every bit difference; 7 bits requires about 200 times, and 5 bits requires 50 times.

## 26 comments on “PWM DAC Design”

1. Davidled
August 17, 2014

Depending on the resolution of PWN, RC value might be changed. PWM frequency is dependent upon clock frequency of microcontroller. I think that determining RC value could be relaying on what type microcontroller is used in the board in order to capture the correct analog information. In addition to that, DAC chip could accomplish the PWM DAC design, or output of microcontroller feeds back to it again, if this contains both ADC and DAC module.

2. D Feucht
August 17, 2014

The purpose of the article is to show what the value of the RC time constant or its corresponding pole should be for n bit resolution – that is, for PWM ripple that is less than 1 LSB for n bits. It does not matter what uC is used. Many CMOS uCs have PWM output capability and within the resolution of the uC PWM resolkution, the output voltage can be generated with a simple RC integrator.

The question then for a designer is: how low does the RC integrator pole have to be below the PWM frequency for ripple that is less than n bits in resolution?

3. dassa.an
August 18, 2014

@DaeJ: Can the temperature be controlled here ? I saw an article where a device which allows the user to control the temperature as wand when required. It also had the customizing facility too.

4. Gibson486
August 18, 2014

The problem I have always had with this method is that you lose your upper and lower bits. That is, when the PWM value is low, the filter sort of stops working (just reads at 0%) and when the PWM value is high, it also stops working (just reads as 100%).  At the end of the day, it is a nice solution if you do dot have a DAC in house or you are VERY tight on space.

5. Gibson486
August 18, 2014

The problem I have always had with this method is that you lose your upper and lower bits. That is, when the PWM value is low, the filter sort of stops working (just reads at 0%) and when the PWM value is high, it also stops working (just reads as 100%).  At the end of the day, it is a nice solution if you do dot have a DAC in house or you are VERY tight on space.

6. antedeluvian
August 18, 2014

Dennis

I have had this issue several times. In the past I have had to dig for a TI or Microchip app note, but none have been as succinct and definitive as this. Thanks.

7. Davidled
August 18, 2014

I think that temperature could be controlled here with other circuit: Temperature is raw analog signal and this data goes into microcontroller through signal condition circuit; and microcontroller will manipulate the data and is requiring the target temperature that user setups in the display screen.

8. Davidled
August 18, 2014

Serial peripheral interface, between PWM output from micro and other chip, could be connected via the pull-up register with VCC (5V or 3.3 V). I am wondering what application could get this benefit by RC formula. DAC chip might be recommended, unless chip is designed. This formula might provide the guideline for the selection of DAC chip.

9. Victor Lorenzo
August 19, 2014

Thanks for the post Dennis, it will be very useful for many of us.

When I started playing guitar I also got very interested in DIY effects processors. A colleague from the department, also a guitar player, came up with the idea of creating a digital echo/delay using a 64kbit RAM memory chip we had at hand, a comparator, a couple of R-C low pass filters (one for the 1 bit A/D and one for the 1 bit D/A). The results were surprisingly good but selecting the cut-off frequency for the reconstruction low-pass filter was critical. Using the same principle, this colleague created an analog output interface for voice synthesis with a very old IBM XT computer.

I've seen also a low power motor closed loop speed control application where a feedback correction (manipulation?) voltage is generated using one PWM output followed by an R-C low pass filter.

10. August 19, 2014

@victor: Is it stable enough ? Im referring to the low power motor

11. August 19, 2014

@Gibson: Thank you for the update mate just one query, what sort of a capacity can it carry ? I presume it's a very small gadget where you can squeeze it in.

12. Victor Lorenzo
August 19, 2014

@chirshadblog, The low power motor is a sensorless brushless motor which includes a very rudimentary controller. The motor speed is directly proportional to its power supply voltage and inverselly proportional to a fraction of its current consumption (which depends on the load).

Speed control is accomplished by using a BUCK DC-DC converter for regulating the motor's supply voltage. By injecting a small voltage into its feedback chain it is possible to control the regulator's output voltage (withing a small range).

The closed loop control strategy is implemented using a modified (simplified) PID controller and timing is controlled by the PID tuning parameters.

One timer channel is used for the PWM output and the other for measuring the current motor speed (using a sensor).

The motor mechanical load has a relatively low inertia and never changes abruptly, only when the whole system is started or shutdown. It outperforms the initial specs and keeps the motor speed in the required range. Some of these systems are still working without interruption from their installation more than five years ago.

13. Davidled
August 19, 2014

Target speed and feedback speed might go to OPAMP comparator that generated Error. System is feedback controller. RC low pass filter is for filtering signal. Low pass filter might be the second order filter which is adding extra R/C in serial pattern. I am not sure that filtering the signal is related closely to n bits formula relating PWM frequency and RC frequency in this article.

14. D Feucht
August 20, 2014

Gibson,

The “loss of bits” at each end of the PWM range is really no loss at all in that the values are exactly what they should be, and without ripple. It is at midscale that the largest ripple occurs.

If the ripple is constrained to be within a LSB (and assuming the PWM generator is linear, which as a digital device should be very linear in time), then the lack of precision of the PWM DAC is largely caused by the resistance of the CMOS output switches which connect the output to either the supply or ground. If a large R value is used to minimize output loading, then this scheme should be good for as many bits as the digital PWM generator itself. The biggest limitation is that the output frequency is limited, rendering this scheme usefual mainly for setting voltage parameters in uC-controlled analog circuitry.

15. vasanjk
August 21, 2014

Dennis,

I would like to know what happens when the frequency chosen is much greater than those factors in the table. For example, I choose a frequency of 200 times for a 10 bit resloution?

Thx

16. samicksha
August 21, 2014

I guess for better operation we need to adjust LPF cutoff frequency such that the residual voltage ripple is less, also increasing PWM frequency can improve DAC response.

17. D Feucht
August 21, 2014

For a switching frequency greater than that given by the table or equation, the ripple is less than an LSB. In other words, the result improves.

18. vasanjk
August 22, 2014

DF

For a given set of RC values, if the frequency selected is higher than specified, would it have an effect on the response time of the resultant analog signal. Will there be a latency between the PWM change and analog signal.

19. D Feucht
August 22, 2014

Vasanjk,

In my previous post, I was referring to the PWM frequency and its effect on the DAC output waveform ripple, though as you noted, the waveform dynamics are also affected by both PWM and DAC output waveform frequencies.

Although the article did not address DAC dynamics, the DAC will have the usual zero-order hold (ZOH) transfer function. The output waveform will be delayed by half the PWM period and as the waveform frequency increases, will roll off (magnitude will decrease) until it is zero at the Nyquist frequency of half the PWM frequency.

The PWM DAC is not known for its dynamic performance yet is a valuable means for minimizing circuitry when a static or near-0 Hz waveform is required, such as setting analog parameters.

20. vasanjk
August 24, 2014

DF

That was an extensive reply. Thanks. By the way, one of my colleagues tells me to use a current source to drive the RC while the PWM waveform is used to switch the current source accordingly. He claims that output voltage linearity would be much improved. Any thoughts on this?

21. D Feucht
August 25, 2014

Vasanjk,

First, there is no point in driving an RC integrator with a current source; the R in series with the source has no effect on circuit behavior because the current source is already an infinite resistance.

As I understand the advice you've been given, the scheme is to switch a current source into (let us say) a capacitor. This resuls in triange-waves instead of the exponential-waves in the article. It would be a good exercise for you or your advisor to work out the equations for this scheme; it is easier than the derivation presented in the article but you can use the article as a kind of template in doing it. (Then submit the result for publication, perhaps.)

I have not done this particular derivation but I think you'll find that the result is not much different than what is in the article. The reason is simple: the exponential ripple is intended to be small and the exponential waveforms are much less than a time constant. This makes them nearly linear, like the triangle-waves of the switched-current scheme. Consequently, I think you can apply the equations of the article as being closely approximate for the suggested scheme.

22. SunitaT
August 31, 2014

Hi Dennis, I must admit that this information proved to be quite useful especially the derivation of the design equation. With everything lined out and well explained, modelling of a simple PWM DAC has been reduced to a simpler task.

23. SunitaT
August 31, 2014

@ DaeJ, that is well explained in brief and concise format.

@ Victor Lorenzo, I was just wondering the maximum number of years an installation based on

24. Victor Lorenzo
September 1, 2014

@SunitaT0, according to customer's requirement, the electronics part is required to work without interruption for at least 10 years. The mechanical part allows routine maintenance (cleaning, oil, etc) once every five years.

25. D Feucht
September 10, 2014

I reviewed the given derivation and noticed that the denominator was approximated by 1 instead of the exponential approximation. When it is used instead, then the result is

D*(1-D)*(Ts/tau) = 2^-n

and (Ts/tau) is not squared because the one in the denominator cancels one of them in the numerator. Then the result is that the x100 ratio for fs/fbw applies to 6 (not 8) bits and this number scales by 2 times per bit. For 7 bits it is x200 and for 5 bits, x50. These more conservative numbers show even more why this is not a fast DAC!

26. sroochi
December 22, 2016

I realize there is more than one way to skin a cat.  Such is the case with DACs.  You can use fully digital  techniques to create precise voltages with respect to a reference by working out the on –off ratios mathematically and implementing them digitally — with simple digital blocks.

A simple way that I use, and uses less overall silicon is to work out binary area ratios of devices and use resistors, capacitors, and even devices — components one have to use anyway to  create and implement any useful device/product.  For example, a simple string of resistors — equal weighted resistors with a simple switching matrix can create without trims, and without complex error correction up to 10Bits (~1024 levels) and with minor complication to ~20Bits. One can even throw in error correction algorithms — especially non-linearity correction–simply and in a very straight forward manner.  The correct design of the basic DAC can be fully monotonic as well so the only need for error correction is the inevitable non-linearity as the design goes beyond 16Bits.

Mixed signal analog-digital design is probably the most powerful design methodology of any that I personally know.  It can create machines of any complexity/intelligence.  By the way, all can be fully computer simulated so one knows for certain that whatever idea you may have created will work first time and every time.

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