The question that arises in the design of a simple PWM DAC is what the low-pass filter pole frequency should be relative to the PWM frequency. This question is addressed by deriving the design equation.
Microcontrollers typically have PWM outputs that can be used as D/A converters when speed is not a constraining design criterion. A simple RC integrator following the output from the μC averages the PWM, where the average voltage is
and D is the duty ratio (or duty cycle) of the PWM output; V is the high-level and full-scale (fs) voltage. For lightly loaded CMOS outputs, it is the supply voltage, VCC . The PWM square-wave from the μC and the RC-integrated waveforms are sketched below with exaggerated ripple.
The voltage ripple is
And the full-scale fractional ripple is
For n bits of resolution, the fractional ripple (as a fraction of fs) is required to be
The exponential vH and vL waveforms follow from basic circuit analysis. The vL (t) waveform during the off-time begins at the peak ripple voltage of vH and exponentially decays toward 0 V, the logic low-level voltage of the PWM output. The time of the minimum vL value is at t = (1 – D)•Ts . Substituting this value for t , the value of vL is
And for vH , the rising exponential begins initially at vL and rises over a voltage range of V – vL toward a target voltage of V . The value of vH is that at t = D•Ts :
Substituting vL into the expression for vH and simplifying,
For Ts /τ << 1, in general, using the first two terms of the Taylor-series expansion of the exp function,
Then the fs fractional ripple and its approximation are
For D = 0 and 1, the ripple is zero and is greatest at D = 0.5. Then
A more convenient ratio than that of time is that of frequency for RC integrator design. The RC integrator pole or break frequency is its bandwidth; ωbw = 1/τ and
Combining these and solving for the ratio,
For n -bit resolution, substitute Δv/V = 2–n . The result is
If solved for the number of bits required, the design formula becomes
From this design formula, for which τ = R•C = 1/2•π•fbw and fs is the PWM frequency, the following table gives the calculated values for an even number of bits of resolution. The numerical pattern is simply that fs /fbw changes by an octave for every bit of change in n.
A mnemonic for remembering the formula is that, for 6 bits, the PWM frequency must be 100 times higher than the integrator pole frequency. Then scale by 2 for every bit difference; 7 bits requires about 200 times, and 5 bits requires 50 times.