Santa Clara, Calif. National Semiconductor Corp. has introduced what it touts as the industry's first quad multipoint-low-voltage differential signaling (M-LVDS) transceiver designed for backplane clock distribution in Advanced Telecom and Computing Architecture (ATCA) and MicroTCA line cards.
The DS91M040 quad M-LVDS transceiver is said to provide the optimum balance of integration and ease of design to reduce board space and design time in end equipment such as wireless base stations, communications routers and LXI test instruments. The quad-channel transceiver is compliant with the EIA/TIA-899 M-LVDS standard.
The DS91M040 drives and receives clock and data signals in multipoint network applications supporting up to four networks simultaneously. It can manage as many as 32 loads at clock frequencies up to 125 MHz and data transfers up to 250 Mbits/s. The transceiver addresses multipoint and multidrop clock and data distribution applications where a common bus connects multiple drivers and receivers.
The transceiver's smooth edges, with 2 nanosecond (ns) typical rise and fall times, minimize signal reflections due to unterminated backplane stubs. A feedback-controlled output provides constant amplitude regardless of whether the backplane is fully loaded or populated with a single card. Both features allow the DS91M040 to deliver the highest noise margin over a wide variety of conditions.
The DS91M040 also includes pin-control of the M-LVDS receiver, which allows designers to enable a receiver failsafe (type 2) or provide no failsafe (type 1) depending on the application. This unique feature reduces a manufacturers' required inventory by eliminating the need to stock two separate transceivers. In addition, the DS91M040 provides an upgrade path to manufacturers that use RS-485 transceivers.
The DS91M040 quad M-LVDS transceiver provides four half-duplex transceiver channels that accept low-voltage transistor-transistor logic (LVTTL) and low-voltage CMOS (LVCMOS) signals at the driver inputs and converts them to differential M-LVDS signal levels. The receiver accepts low-voltage differential signals such as LVDS, Bus-LVDS, M-LVDS, low-voltage positive-emitter-coupled logic (LVPECL) and common-mode logic (CML) and converts them to 3-V LVCMOS signals.
The DS91M040 supports both M-LVDS type 1 and type 2 receiver inputs and shields adjoining circuits with 15 kV of electrostatic discharge (ESD) protection on the M-LVDS input/output (I/O) pins. The separate enable controls for each channel provide designers with maximum flexibility because each channel can serve as a driver or receiver, or may be shut down for lower power consumption. The DS91M040 is offered in a 5 x 5-mm, 32-pin LLP package.
National Semiconductor , www.national.com