Can I bootstrap a low-voltage amplifier to get a higher-voltage buffer?
I was designing the input of a precision voltmeter and needed a sub-picoampere input unity-gain amplifier/buffer with less than 1 µVP-P low frequency noise, a low offset voltage of approximately 100 µV, and a non-linearity of less than 1 ppm. It also needed to have very low AC distortion over audio frequencies and 60 Hz to make use of ever-deepening ADC resolution. That’s ambitious enough, but it must buffer ±40 V signals using ±50 V supplies. The buffer input would be connected to either a high-impedance divider or directly to external signals. Thus, it must also tolerate electrostatic discharges (ESD) and inputs beyond the supplies.
There aren’t many sub-picoampere bias current op amps available. Those that are available are often called electrometer grade and offer low tens of femtoampere bias current. Those electrometer amplifiers, unfortunately, have a low-frequency noise (0.1 Hz to 10 Hz) of several microvolts peak-to-peak. They also generally have input offset voltage and offset temperature coefficients that don’t meet requirements. Their common-mode rejection ratio (CMRR) and open-loop gain aren’t good enough to support 1 ppm linearity. Finally, none of the electrometers can tolerate high supply voltages.
The LTC6240 family offers 0.25 pA typical bias current and 0.55 µV p-p low frequency noise. That’s good enough for the input buffer except that the part only works on supplies up to 12 V maximum. We will have to add circuitry around the amplifier to adapt it to higher voltages.
Figure 1 shows a simplified schematic of a bootstrapped amplifier.
Because the supplies always follow the input signal, as buffered by the output of the LTC6240, there is no common-mode input error at all, ideally. Even a mediocre CMRR is bootstrapped up by at least 30 dB. That 30 dB value is due to the finite gain accuracy of the VP and VM buffers.
The open-loop gain of the LTC6240 also gets a boost. Gain limitations in amplifier circuits arise when transistor output impedances exist between an internal gain node(s) and a power-supply rail. Because the supplies are bootstrapped to the output, little signal current flows through said impedances, and open-loop gain is raised by amounts like the CMRR benefit. Loading of the output can, however, still limit open-loop gain.
Less obviously perhaps, bootstrapping also raises the overall circuit slew rate. Normally, internal LTC6240 quiescent currents and compensation capacitors referenced to supplies limits slew rate. When the supplies follow the input and output, little dynamic current flows into these capacitors and the amplifier never enters limited slew rate. The buffer amplifiers will ultimately limit overall slew rate.
The high voltage supplies VHVP and VHVM may have disturbances, but the buffer outputs will largely reject them, greatly enhancing the LTC6240 power-supply rejection ratio (PSRR).
So, this is great; the buffer is improved in several ways by bootstrapping the supplies. What could go wrong? Well, the circuit shown in Fig. 1 will almost certainly oscillate. The best way to think of the supply terminals’ behavior is as part of a feedback loop: the output terminal voltage times the buffer amplifier frequency response, then times 1/PSRR is added to the input, finally multiplied by the open-loop gain to become the output, and around the loop evermore. Figure 2a shows the PSRR over frequency.
We don’t get phase data in our PSRR plot, but let’s say it has a +90° phase. Yes, that’s +90° like a differentiator. The open-loop gain, seen in Figure 2b, has a –90°phase from low frequencies to 100 kHz, after which it becomes increasingly negative. The buffers will have finite frequency response and they will exhibit phase lag as well. Adding up all the phase lags in the loop guarantees a few frequencies wherein the feedback phase is 0° or multiples of 360°. If the supply loop gain is less than 1 at such phases, we have an oscillator. The PSRR magnitude drops to a low of 4 dB (that’s attenuation = –4 dB → gain = 0.63 in non-dB) so it appears that the loop might never have enough gain to oscillate. That’s probably wrong, since the PSRR applies to both VP and VS, and their PSRR gains may well add up to a magnitude more than one. Further, the buffers could have some peaking before their gain rolls off at high frequency, pushing the overall feedback magnitude of greater than 1. We will also see that the buffers must drive moderately large capacitors and will have more phase lag. In any event, simulating the circuit in LTspice showed large signal oscillations (the frequency response and nonlinearities of the LTC6240 are embodied in the macromodel).
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