Figure 3 shows the full circuit.
Note the 1000 pF bypass capacitors must be closely connected to the LTC6240 supply terminals. Op amps have dozens of internal transistors that, in this amplifier, have Ft’s on the order of GHz. They are often connected in feedback to each other and, unless you install bypass capacitors, can oscillate against a high AC impedance supply. A 1000 pF capacitor will quash those oscillations. We also want the supply bypass capacitor to be much greater than any output load capacitor. At high frequencies, voltage transitions across a load capacitor cause currents that flow to a supply rail and can modulate the supply voltage, feeding back through PSRR to cause oscillation. Our bypass capacitors thus reduce supply modulation at frequency, equivalent to reducing feedback gain from output to supply.
Slewing those bypass capacitors will take serious current and must be bidirectional. Q5 and Q6 are emitter followers that can drive the bypass’ slew currents. Q3 and Q4 are biasing diodes to set Q5 and Q6 quiescent currents. Q2 provides the bias current for those diodes and for Zener D1 (really a shunt reference IC), which sets a positive supply voltage relative to the output. Q2’s collector is the output of a current mirror biased by R9 between the high voltage rails. R9 might be replaced with two current sources if the supply voltages are not constant.
Q7 through Q12 form the VM minus supply driver equivalent to the previous description. Note the intentional mismatch in the Zener voltages: 5 V above the input/output for VP and 3 V below input/output for VM. The mismatch centers the input voltage within the LTC6240’s supply-limited input range to optimize slew waveforms.
Normally, the supply current of the LTC6240 pulls against Q5’s emitter and substantially turns off Q6, so that the VP buffer output impedance is mostly R3. The bandwidth of the supply feedback VP path is thus ~1/ (2π × 100 Ω × 0.001 µF) = 1.6 MHz. This guarantees that the VP loop gain is substantially less than one around 10 MHz and above, where LTC6240 open-loop phase is moving toward oscillation. The 100 Ω resistor also allows follower Q5 to not have to drive the 1000 pF directly. Emitter followers display output inductance that can resonate with capacitive loads, causing ringing or even oscillations.
Having designed the bootstrapping to fail at frequencies above 1.6 MHz, we will see that perfect behavior of the overall circuit will degrade beyond ~100 kHz. If the output cannot exactly follow the input, the benefits of bootstrapping degrade. RIN with CIN limits bandwidth to 100 kHz, part of a system anti-alias filter for an ADC to follow the buffer, and it also attenuates radio interference and unsupportable slew rates.
The circuit must tolerate any unlimited-slew input signal or ESD, so RIN also serves to limit input fault current. The resistor has four series segments to split up input overdrive and tolerate 1 kV temporarily. Depending on the signal source and anticipated overloads, the input resistor can be reduced.
There are protection diodes within the LTC6240 that guide input overvoltage currents to either VP or VM. The maximum fault current allowed into the LTC6240’s input is 10 mA, but if there is surrounding circuitry that can quickly disconnect the input fault, that current can be increased for a short time. In the intended application of this circuit, there is an SPDT relay that, when unpowered, connects the input of the buffer to a divide-by-ten network. When powered, the relay connects the input directly. Thus, when unpowered the buffer connects to much more than 10 kΩ source impedance and the fault voltage and current are reduced commensurate with that 10 mA continuous rating. The input range of my application is continuously ±400 V with a fault tolerance of ±1000 V. This can only be safely done if there are two comparators that sense input overvolt- age and quickly release the relay. This can be done in 1 ms to 2 ms, allowing a transient 100 mA input current that will not melt the protection diodes of the LTC6240. Note the inclusion of D3 through D6 to guide the input overload current which had been directed to VP or VM through the LTC6240 to the VHVP or VHVM supplies. These supplies probably cannot absorb the overload current since that current is backward to normal supply operation; we would depend on large enough bypass capacitance to hold the supply voltage safely while waiting for the relay switch relief. We would need 100 µF to hold the supply to within a 2 V change in 2 ms from a 100 mA overload.
Part 2 (Monday, September 30) covers the high-voltage signal source, measurement setup, and test results.