Reduce clock network design effort with zero delay generators

Hillsboro, Ore. — Lattice Semiconductor Corp.'s second generation of enhanced zero-delay clock generators for high performance communications and computing applications can generate up to 20 clock outputs.

Each output offers independently programmable output skew, I/O standard and frequency selection. The ispClock5600A's phase-locked loop (PLL) and divider systems supports the synthesis of multiple clock frequencies derived from the reference input through the provision of programmable input and feedback dividers. The non-volatile, in-system programmable E2CMOS -based ispClock5600A devices are pin compatible with Lattice's first generation ispClock5600 devices, but provide a number of significant additional features and parametric enhancements, the company said.

The maximum voltage-controlled oscillator (VCO) operating frequency of the ispClock5600A devices has been increased to 800 MHz. This supports 33.33 MHz, 100 MHz, 133.33 MHz and 50 MHz clock frequencies simultaneously from a single master frequency. The input clock frequency range has been extended (5 MHz to 400 MHz) to enable support at 8.192 MHz. Additionally, the device's universal fan-out buffer is able to source clocks to DDRII and QDRII memories (up to 400 MHz).

The ispClock5600A devices use seven on-chip counters (input, feedback and five for outputs) to provide fine granularity output frequency generation. The high-performance universal fan-out buffer has a maximum pin-to-pin skew of 50 picoseconds, regardless of bank and frequency, while the maximum cycle to cycle (peak to peak) output jitter is less than 70 ps, and the period jitter less than 12 ps (rms). The output skew of each clock net relative to the reference input can be further controlled in delay increments of 156 ps (lead or lag) to compensate for differences in circuit board clock network trace length.

In addition, both the reference input and the universal fan-out buffers can support a wide variety of popular single-ended and differential logic standards (LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL, Differential HSTL, Differential SSTL) at a variety of voltage levels. The input termination and output impedance of each output can be individually tuned to match each trace impedance, resulting in clock nets with high signal integrity.

The Lattice Windows-based design software, PAC-Designer Version 4.1, provides comprehensive design support for the ispClock5600A device family.
This version of the PAC-Designer software can be downloaded for free .
PACsystemCLK5620A evaluation kits also are available through Lattice distributors or on the Lattice site for $295.

See related block diagram

The ispClock5620A , packaged in a 100-pin TQFP, is available now in both commercial and industrial temperature grades. Pricing for the first available device, the ispClock5620A , start at $6.80 in 10,000-piece quantities. Click here for the ispClock5620A data sheet .

Lattice Semiconductor , 1-503-268-8739,

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