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Reducing EMI in digital systems using spread spectrum clock generators (Part 2 of 2)

[Part 1 looked at the basic operation and spectrum impact of spread spectrum clock generators; you can read it here .]


Types of spread

Based on the position of start and stop frequencies with respect to reference frequency, SSCGs can be classified in the following three categories:

  1. Down Spread: Modulates the reference clock downwards and restricts the maximum frequency of the modulated signal to the frequency of reference clock. Useful in applications which are frequency sensitive and are already operating at the maximum rate they can operate.

Down spread (%) = (Δf / fo ) × 100,

where Δf = fref – fmin

A down spread provides the spread spectrum clock while maintaining the maximum allowed frequency in the system.


  1. Center Spread: Modulates the output clock symmetrically about the reference frequency (i.e., the output frequency will increase and decrease the same amount above and below the center frequency). A 1% center spread will provide a total variation of 2% with 1% variation above and another 1% below the reference frequency.

Center spread (%) =   ½ (Δf / fo ) × 100,  

where Δf = fmax – fmin

Center spread is useful in systems where the frequency restriction doesn’t apply.

  1. Up Spread: Up-spread is exactly opposite down-spread. The reference clock is modulated upwards by restricting the lower limit to reference clock.

Up spread (%) = (Δf / fo ) × 100,             

where Δf = fmax – fref


Precautions when using spread spectrum clock:


  1. Jitter:

One of the significant disadvantages of using a spread spectrum clock is that it cannot be used in systems where clock accuracy is of major concern; e.g. for Ethernet or CAN bus applications. Engineers must take special care in selecting spread clocks and the spread amount for their application requirements as it may introduce substantial jitter number to the clock signal. This jitter may adversely affect system performance, causing critical setup and hold time violations, higher bit error rates, and PLL unlock issues. Jitter can be of different types and can have different effects on the performance of a system.


  1. Period Jitter (PJ): PJ refers to the maximum change in a clock’s output transition from its ideal position. PJ is generally measured as the peak-to-peak period variation evaluated over time, typically ten thousand cycles, which is simply the difference between the earliest and the latest edge. Period jitter can impact the performance of a synchronous system by reducing the timing budget. The variation of clock period from its ideal position may also lead to data setup and hold time violations.

A 100 MHz clock signal modulated with 1% up-spread will have a total frequency variation (Δf) of 1 MHz, with a start frequency being 100 MHz and stop frequency 101 MHz. This corresponds to variation in period from 9.9ns to 10ns. As a result, the ideal spread clock will have peak-to-peak period jitter of 0.1ns (100ps). As the spread amount is increased or the clock frequency increments keeping the spread fixed, the total frequency variation increases proportionally, hence the PJ may violate certain timing parameters.

One must note here that the PJ mentioned here is solely the one introduced due to the spread clock. The device itself may add its own intrinsic jitter, making the total jitter higher than estimated above. The intrinsic jitter of device may be measured by turning off the spread.


  1. Long-Term Jitter (LTJ) : LTJ is similar to period jitter but represents the maximum change in a clock’s output transition from its ideal position over many cycles. Although it is applicable to a few specific applications, it becomes crucial with spread spectrum signals where the timing edges could be significantly displaced in time from their ideal locations. The best example of a problem with LTJ can be seen on a graphics card driving a display: excessive LTJ may cause the pixel data to be shifted from its desired position over a span of time.
  1. Cycle-to-Cycle Jitter (CTCJ): CTCJ is another jitter type defined as the change in clock’s output transition from its corresponding position in the previous cycle. CTCJ is mostly undesirable in communication systems or in ADC circuits where the input signal is sampled at a particular instance and digitized according to the sampled value.

CTCJ in a sampling clock may cause the input to be sampled away from the desired instance, leading to a bit error in the output data stream. The spread spectrum clock actually introduces an insignificant amount of CTCJ to the clock. With a very slow modulation rate, between 30 kHz to 120 kHz (which is at least one thousand times slower in comparison to the reference clock frequency) it takes more than a thousand clock cycles to complete one modulation cycle, leading to negligible period differences between adjacent cycles.

However, the device itself might add its own intrinsic CTCJ to the output clock. Spread spectrum techniques contributes less than 0.05% of CTCJ to the system. Thus, an SSCG may be well-suited for systems requiring low CTCJ, low bit error rates, and low EMI.

  1. Spread spectrum with PLL :

Another area where extra precautions must be taken is in designs where a PLL device is a downstream and driven by the spread clock. A PLL exhibits the characteristics of a low-pass filter which allows the low-speed variations in the input frequency to be passed, while attenuating high-frequency changes above its bandwidth.

Since the spread spectrum purposefully modulates the clock, the PLL may have trouble maintaining the lock to the input spread spectrum clock. The downstream PLL must be able to track the frequency change to pass the modulated clock. This depends on the PLL’s bandwidth. If the PLL’s bandwidth is too low, the PLL will not reliably track the input signal, resulting in tracking skew which in turn adds more jitter to the system.

Programmable SSCGs:

Programmability provides flexibility and easy inventory management. With a programming option available on a clock generator chip such as configurable drive strength, system designers can easily change the drive strength (rise/fall time) of the clock edge based on application requirements. This may be helpful in further reducing EMI.


There are SSCGs in market with more conciliatory programming options, where system designers can change parameters such as spread amount, spread profile type, spread on/off, type of spread and output clock frequency. Another major advantage of the programmable SSCG is that multiple, unique programmable-frequency outputs can be integrated into a single chip, thus eliminating the large number of crystals and reducing the overall cost. Depending upon the application, designers can use a single SSCG to provide clocks with different properties to each subsystem, resulting in faster time to market and lower cost.


About the authors

Ashish Kumar is presently working with Cypress Semiconductor India Pvt. Ltd. as a Senior Product Engineer. His interests are in making hobby electronic projects, debugging circuit boards, and dealing with complex analog and digital circuits.
Pushek Madaan is currently working with Cypress Semiconductor India Pvt. Ltd. as a Senior Application Engineer. His interests lay in designing embedded system applications in C and assembly languages, working with analog and digital circuits, developing GUIs in C# and, above all, enjoying adventure sports. Pushek can be reached at pmad@cypress.com.

1 comment on “Reducing EMI in digital systems using spread spectrum clock generators (Part 2 of 2)

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    August 21, 2015

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