The current-mode or peak-current-regulating switching converter is a familiar, almost dominant, power supply circuit consisting of few parts and is usually designed with “cookbook” procedures from PWM-controller IC manufacturers. Yet it is one of the most complicated “simple” circuits around. This multipart article descends slowly into the depths of its complications a few layers, so that you can choose how deeply you want to understand it. When taken a step at a time, it is quite understandable, though there are many steps to a complete understanding.

The basic converter circuit structure is shown here as a common-passive (CP or buck) converter, though it could be any of the three basic *PWM switch* converter configurations: CP, CA (boost), or CL (boost-buck).

The PWM switch is simply the on-time and off-time switch in series with the inductor. It forms a three-terminal circuit element that can be analyzed (and even linearized, as we will do later) as an active device. During the on-time, *t _{on} * , in the active (A) switch position,

*Q*conducts. During the off-time,

*t*, what is effectively a single-pole, double-throw (SPDT) switch switches to the passive (P) switch position, and the diode conducts.

_{off}To summarize the circuit, the power switch, *Q* , is in series with a sense resistor, *R _{S} * . A current-sense amplifier provides a voltage,

*v*, proportional to inductor (

_{iL}*L*) current.

*v*is input to the PWM comparator, where it is compared to an input error voltage,

_{iL}*v*, from the voltage-regulating outer loop. The comparator resets a flop to end the on-time of the switching cycle when the current waveform, which is essentially a ramp, reaches its peak value set by

_{V}_{e}*v*. In other words, when

_{V}_{e}*v*=

_{i}_{L}*v*, the comparator changes state and resets the flop, turning off the power switch. An oscillator that sets the switching frequency,

_{V}_{e}*f*, sets the flop to start both the on-time interval and the switching cycle.

_{s}Furthermore, the circuit can be decomposed into the *power stage* and the control circuits operating it. Shown below is the simplified power stage (right) and the equivalent PWM-switch power-stage circuit (left).

The outer loop is a continuous feedback loop that can be analyzed with the classic feedback control theory of analog circuits textbooks and of continuous or (as we call them) *linear* power supplies. This is possible because the bandwidth of this loop, *f _{bw} * <<

*f*, and the switching activity occurs so frequently that the voltage-regulating loop waveforms can be considered continuous (analog).

_{s}The inner current loop is quite different. It is not linear in that it has within it one function (one block in its block diagram) that is digital: the SPDT PWM switch, consisting of the MOSFET when on and the diode when off. The resulting nonlinearity is of a kind that can be handled with linear (*s* -domain) circuit theory because it is *piecewise-continuous* . The discontinuities are only at the switching events that are (ideally) points in time. The regular starting times of the switching cycle have within them time-varying comparator switching events that make the circuit *time-variant* . This means that it is a different circuit when *t _{on} * varies, and the time variation is characterized by the circuit parameter, the

*duty ratio*(or

*duty cycle*),

where *T _{s} * is the switching period;

*f*= 1/

_{s}*T*,

_{s}*t*= the on-time of

_{on}*Q*and

*t*= the off-time of

_{off}*Q*. The duty ratio is expressed in the general case as a

*total variable*, δ, which is the sum of a constant or large-signal operating-point value,

*D*, and an incremental value of variance about

*D*of

*d*;

The kind of variable that δ is is a parameter: an independent circuit variable held constant (as *D* ) while the current and voltage waveforms are analyzed with circuit theory. However, it changes slowly relative to the behavior within the current control loop, and this condition is the converter *steady-state* condition, where δ = *D* and the circuit is time-invariant. Consequently, the switching events are like sampling events in sampled circuits, which also are nonlinear because of the sampling. However, sample-and-hold circuits are analyzed in the linear, time-invariant *s* -domain in circuits books, and PWM-switch circuits can be, too.

Around 1990, Ray Ridley discovered that this circuit could be thought of as a sample-and-hold or *zero-order hold* (ZOH) *sampling* circuit, though it is not the usual capacitor voltage-sampling circuit. It is the dual; the inductor samples the current and holds its incremental or small-signal value — the change from the previous cycle — during the off-time. Ridley proceeded to work out a sampled-loop model for it as his PhD thesis. A fellow PhD student, Richard Tymerski, also at VPI with Vatché Vorpérian as his adviser, discovered that the three basic switching converter schemes were the three configurations of the PWM switch. (The late 1980s was a good time for converter theory.)

Before Ridley's sampled-loop equivalent circuit model (or what he called the “continuous-time” model, though it is actually piecewise-continuous), the first-generation modeling of this “simple” circuit was advanced largely by RD Middlebrook, the renowned CalTech EE professor, as “state-space averaging.” It is explained in the classic power-electronics textbook by Erickson and Macsimović (*Fundamentals of Power Electronics* , Kluwer) and is the *low-frequency average* (lf-avg) model. It analyzes the circuit without regard to sampling, much as the outer voltage loop can be analyzed. Consequently, it does not include (as does the sampled-loop model) the *subharmonic oscillation* that can occur in the converter, where alternating cycles have a different duty ratio. In the sampled-loop model, a peak in the amplitude response of the loop shows up at the Nyquist frequency, *f _{s} * /2, that can indicate an unstable feedback loop.

Before we can apply sampling theory to the peak-current-loop circuit, it is first linearized to bring in familiar *s* -domain analysis. This involves derivation of an incremental model for the PWM-switch.

I've enjoyed many an argument about how the inner current loop actually works. Arguing about the theory is one thing, but the real issue with current-mode control is the quality of the current sense signal. It's very difficult to get a great signal-to-noise ratio and accurate current reporting. I admire your willingness to take this on and I will be reading very carefully, thank you for addressing this subject, it truly is an interesting one.

Ken,

I am encouraged by your interest in both the theoretical and practical aspects of current-loop converters. What is strange about the theoretical development is that the older contributors to its advancement are no longer active in pressing forth on its development:

R.D. Middlebrook is dead; F. Dong Tan I cannot even find.

Richard Tymerski is doing control theory not directly related to current-loop development. Duwang Li is in industry, working for CUI.

Ray Ridley is giving courses on it, but is still back where his doctoral thesis brought the field. He seems to be convinced that it is adequate. For design, I partially agree, though the theory has been made more comprehensive, simpler, and with more insight than in the early '90s.

I cannot find anyone at MIT who is into it. Professor Perreault was helpful in giving me some leads. Erickson and Macsimovic have not answered my emails, nor has Vatche Vorperian at VPI. I haven't contacted Free Lee.

Robert Sheehan and Tom Hegarty at TI are about the most involved of anyone. And I should also include Christophe Basso of ON Semi in France.

So … anyone who shows a serious interest in development of what I call the “refined theory” I take an interest in! Few are because it takes some work to go through it, and some understanding of DSP (z-domain or sampling theory) and control theory.

This six-part series does not present the complete theory. What I have intended to do is to establish the basic principles, such as the waveform dynamics, linearization of the PWM switch and the control modeling of the loop itself. From this, one is prepared to read the fuller development, which starts in a series of articles at

http://www.how2power.com/newsletters/1109/index.html

So read through the Planet Analog series, then if you are still interested in going farther, try the above series.

Hi Dennis, just to encourage you: Good that you picked this one. Indeed it is a nasty one. Peeling the circuit off shell by shell is the only way to really understand this one. For younger engineers out there a *must follow*, I would say. I am sure you have a good method about to get the control opamp circuitry explained, can't wait 😉

Nav-

I hope that I do not disappoint you in that “control op-amp circuitry” is usually found in the outer voltage-regulating loop. To understand it – a continuous, unsampled part of the overall converter – ordinary classical control theory of the kind that is presented in undergrad active-circuits textbooks is sufficient. At least the principles are there, and can be found more clearly explained in most introductory control theory textbooks.

But the inner peak-current control loop – that is more complicated, though it has few parts. This series is about it. Perhaps in the future I will do a series on ordinary feedback control because its application to circuits can be explained more clearly than it is in most textbooks. I have not written articles about it because I already did in my book,

DesigningAmplifier Circuits, atsci.presswarehouse.com/Books/SearchResults.aspx?str=Feucht

The dynamics of feedback loops continues to be developed in the succeeding volumes, especially in

Designing Dynamic Circuit Response.NOTE OF CORRECTIONS: Two name typos in my previous entry:

“Tom Hegarty” should be Tim Hegarty

“Free Lee” should be Fred Lee. My apologies to both persons for my bad typing.

To analyze this circuit, engineer could simulate this circuit in the pspice. Once fully understanding it, this circuit could be used to any application. Possibly, as one of application, current might be measured cross Rs. It could be imaged that this circuit could be used in the measurement tool.

Thanks Dennis for bringing us this series. This converter represents one of those apparently simple circuits that become surpricingly complex to fully characterize and understand. in converters theory and design we must go far beyond calculating some operating points and some time constants and doing some SPICE simulations.

I am looking forward to descending for the next layer.

Understanding will be effective if it is done in the correct way. Because it can increase the effectiveness of the application. Wrong understanding may cause for a loss.

enjoyed the discussion too.although the content is comlocated the effective understanding will help to sort out the matters easily

Dennis, I wonder if categorizing the V feedback and I feedback into categories helps in understanding, or hurts. What I'm thinking: if the V feedback and I feedback add together in the same direction, that's simply a gain modulation thing. If, in any case, the I feedback subtracts from the V feedback, well, that's a gain degradation. I'm not explaining my thougth very well. Regardless, I'm not sure if the feedback is so complex and variable depending on operating state, that a simplification aids proper analysis or leads off into the weeds.

Ken,

I find it vastly simplifying to formulate the circuit analysis with the nested loops. So have major contributors in the past. Ridley's breakthrough paper of the early 1990s does this. By separating the current and voltage control loops, an example of problem reduction occurs, by decomposing it into two separate control problems to be solved: first the inner current loop, then the outer loop. The current loop is thus a block in the overall voltage loop, and as we will see in later parts of the article, it affects behavior around the Nyquist frequency – relatively high-frequency behavior relative to the switching frequency. The voltage loop bandwidth is much below this, and consequently separates in frequency the effects of each of the loops.

Dennis, Thanks for the converter series… Very eager to learn and understand current and voltage feedback modes. Will hope to learn the compensation for these feedback networks.

“… current and voltage feedback modes.”

A

modeis a change in circuit structure. The analysis of this series is for the peak (or valley) current-controlled converter with an outer voltage control loop. There is such a thing as avoltagecontrolled converter, wherein the output voltage controls the PWM duty ratio, but that is a different control scheme than the one being developed here. In the scheme developed here, the duty ratio is controlled by the peak current, which controls the converter power-stage output current, which affects the voltage, which is fed back and affects the peak current level that affects the duty ratio, thus closing the loop.