The current-mode or peak-current-regulating switching converter is a familiar, almost dominant, power supply circuit consisting of few parts and is usually designed with “cookbook” procedures from PWM-controller IC manufacturers. Yet it is one of the most complicated “simple” circuits around. This multipart article descends slowly into the depths of its complications a few layers, so that you can choose how deeply you want to understand it. When taken a step at a time, it is quite understandable, though there are many steps to a complete understanding.
The basic converter circuit structure is shown here as a common-passive (CP or buck) converter, though it could be any of the three basic PWM switch converter configurations: CP, CA (boost), or CL (boost-buck).
The PWM switch is simply the on-time and off-time switch in series with the inductor. It forms a three-terminal circuit element that can be analyzed (and even linearized, as we will do later) as an active device. During the on-time, ton , in the active (A) switch position, Q conducts. During the off-time, toff , what is effectively a single-pole, double-throw (SPDT) switch switches to the passive (P) switch position, and the diode conducts.
To summarize the circuit, the power switch, Q , is in series with a sense resistor, RS . A current-sense amplifier provides a voltage, viL , proportional to inductor (L ) current. viL is input to the PWM comparator, where it is compared to an input error voltage, vV e , from the voltage-regulating outer loop. The comparator resets a flop to end the on-time of the switching cycle when the current waveform, which is essentially a ramp, reaches its peak value set by vV e . In other words, when vi L = vV e , the comparator changes state and resets the flop, turning off the power switch. An oscillator that sets the switching frequency, fs , sets the flop to start both the on-time interval and the switching cycle.
Furthermore, the circuit can be decomposed into the power stage and the control circuits operating it. Shown below is the simplified power stage (right) and the equivalent PWM-switch power-stage circuit (left).
The outer loop is a continuous feedback loop that can be analyzed with the classic feedback control theory of analog circuits textbooks and of continuous or (as we call them) linear power supplies. This is possible because the bandwidth of this loop, fbw << fs , and the switching activity occurs so frequently that the voltage-regulating loop waveforms can be considered continuous (analog).
The inner current loop is quite different. It is not linear in that it has within it one function (one block in its block diagram) that is digital: the SPDT PWM switch, consisting of the MOSFET when on and the diode when off. The resulting nonlinearity is of a kind that can be handled with linear (s -domain) circuit theory because it is piecewise-continuous . The discontinuities are only at the switching events that are (ideally) points in time. The regular starting times of the switching cycle have within them time-varying comparator switching events that make the circuit time-variant . This means that it is a different circuit when ton varies, and the time variation is characterized by the circuit parameter, the duty ratio (or duty cycle ),
where Ts is the switching period; fs = 1/Ts , ton = the on-time of Q and toff = the off-time of Q . The duty ratio is expressed in the general case as a total variable , δ, which is the sum of a constant or large-signal operating-point value, D , and an incremental value of variance about D of d ;
The kind of variable that δ is is a parameter: an independent circuit variable held constant (as D ) while the current and voltage waveforms are analyzed with circuit theory. However, it changes slowly relative to the behavior within the current control loop, and this condition is the converter steady-state condition, where δ = D and the circuit is time-invariant. Consequently, the switching events are like sampling events in sampled circuits, which also are nonlinear because of the sampling. However, sample-and-hold circuits are analyzed in the linear, time-invariant s -domain in circuits books, and PWM-switch circuits can be, too.
Around 1990, Ray Ridley discovered that this circuit could be thought of as a sample-and-hold or zero-order hold (ZOH) sampling circuit, though it is not the usual capacitor voltage-sampling circuit. It is the dual; the inductor samples the current and holds its incremental or small-signal value — the change from the previous cycle — during the off-time. Ridley proceeded to work out a sampled-loop model for it as his PhD thesis. A fellow PhD student, Richard Tymerski, also at VPI with Vatché Vorpérian as his adviser, discovered that the three basic switching converter schemes were the three configurations of the PWM switch. (The late 1980s was a good time for converter theory.)
Before Ridley's sampled-loop equivalent circuit model (or what he called the “continuous-time” model, though it is actually piecewise-continuous), the first-generation modeling of this “simple” circuit was advanced largely by RD Middlebrook, the renowned CalTech EE professor, as “state-space averaging.” It is explained in the classic power-electronics textbook by Erickson and Macsimović (Fundamentals of Power Electronics , Kluwer) and is the low-frequency average (lf-avg) model. It analyzes the circuit without regard to sampling, much as the outer voltage loop can be analyzed. Consequently, it does not include (as does the sampled-loop model) the subharmonic oscillation that can occur in the converter, where alternating cycles have a different duty ratio. In the sampled-loop model, a peak in the amplitude response of the loop shows up at the Nyquist frequency, fs /2, that can indicate an unstable feedback loop.
Before we can apply sampling theory to the peak-current-loop circuit, it is first linearized to bring in familiar s -domain analysis. This involves derivation of an incremental model for the PWM-switch.