Scientists and neural researchers have been probing the brain (human and other animals) for quite a few years in an attempt to learn how it works and fix what goes wrong. Based on recent integrated circuit work, researchers should have a better, higher resolution way to gather information soon.
A recent IEEE/ISSCC paper shows the way to integrate the microprobes that contact brain cells with the IC that processes the information. The microprobes are fabricated with multiple layers with the outermost being platinum over titanium. Figure 1 shows what the probes look like. Length is about 150μm. (This image and all others are taken from the paper.)
The probes are made by etching away the unwanted silicon and vapor depositing the metal — standard techniques for IC fabrication.
The beauty of the design is that the processing circuitry is right next to the probes (on the other side of the chip, actually). That circuitry consists of the expected passive components, through-silicon-vias (TSVs), and the active circuitry. The vias connect the probes to the active circuitry. Figure 2 shows a bit of detail.
This eliminates the usual long wires carrying weak signals from probes to circuit boards where the amplifiers would normally process those signals.
The authors provide some additional details on how elements are interconnected and some dimensions:
MEMS neural microprobe array and low-power CMOS readout circuit are fabricated on two sides of the same silicon substrate, and TSVs are used to form a low impedance interconnection between the microprobe and CMOS circuitry, thus providing the shortest signal transmission distance from sensors to circuits. The low parasitic impedance of TSV minimizes transmission loss and noise. The overall chip is 5x5mm2 , 350μm in thickness including 150μm probe height and 200μm TSV height, respectively. A total of 480 microprobes is divided into 4×4 sensing areas, forming 16 channels.
Leakage current on the chip from any one TSV to another nearby TSV (200 μm apart) is on the order of a few pA. The TSVs show good conduction (5.5mΩ) and extremely low parasitic capacitance (around 34fF), measured up to 10GHz.
All this combines to produce a circuit without the usual IR-drop and noise pickup problems associated with the usual long cabling. The active circuitry on the chip is fairly recognizable analog front end (AFE) that most analog engineers will know as that used with EEG applications:
The IC has additional biasing and current mirror circuitry onboard.
This IC exhibits very good CMRR and has low noise. These are probably the two most important criteria for these applications.
References 1. ” Through-Silicon-Via-Based Double-Side Integrated Microsystem for Neural Sensing Applications” by Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, and Ho-Ming Tong; published by the IEEE as part of the International Solid-State Circuits Conference. Registration required for viewing or downloading documents.