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Separating linear from slew limited performance in amplifiers (Part 1 of 2). The signal sped up, insight #14

As long as the output step does not slew limit, the rise time will be constant with step size at 0.35/F-3dB or 0.35/5.28MHz = 66nsec in this gain of +4V/V configuration. Occasionally, this linear “fixed” rise time is divided into an increasing output step size to produce a plot of increasing “slew rate” with step size (Figure 25, reference 4).  This is another case of confusing rise time with slew rate.

The OPA1678 data sheet (Ref. 2) quotes a 9 V/μsec slew rate in an inverting gain of -1V/V. This would be an output stage slew rate limit where a gain of +4V/V should approach that limit.

Solving eq. 2 for VSTEP with F-3dB = 5.28MHz and a 9V/μsec SR yields <0.74 V output step to theoretically stay non-slew limited if the 10% to 90% line fit is representative of output slew rate. Reducing that slightly to a 0.625V output VSTEP in Figure 4 shows what looks like a first-order step response along with a small +0.74mV input offset voltage in the TINA model.

Figure 4. This looks like a 1st order ±0.3125V band-limited output step response.

Expanding the rising edge in Figure 5 and placing markers at -0.25V and +0.25V, the 10% to 90% rise time is 70nsec suggesting an average slope of 0.5V/70nsec = 7.1V/μsec.

Figure 5. Expanding the edge shows a rise time of 70nsec using a 10% to 90% line fit slope.

There are actually three regions in this edge response –

  • An initially very fast dV/dt rate set by ≈(VSTEP/τ) for the first-order model (=20.8V/μsec)
  • This quickly breaks off to the available slew rate since this initial peak dV/dt far exceeds the available slew rate in the model.
  • An exponential tail to zero as the instantaneous dV/dt falls below the modeled slew rate.

Zooming in on the rising edge at 2μsec for this 500kHz square wave shows these three regions in the spot dV/dt plot of Figure 6.


Figure 6. Spot dV/dt over the rising edge shows three distinct regions.

While it is often difficult to pick off the peak dV/dt in a step response waveform, the point slope plot shows the regions clearly. Here, this output step is slew limited at +8.7V/μsec shown by the flat portion of this spot dV/dt curve. This is slightly below the inverting gain of -1V/V specified 9V/μsec as this non-inverting gain of +4V/V approaches that limit.

This simulated response starts out at dV/dt = 0 due to the second pole in the small signal response. It then rises towards a greater than SR peak approximated by VSTEP/τ. That quickly reduces to the available output slew rate and then eventually decays to zero as the step finds a final value. This OPA1678 model is doing a great job of transitioning from slew limited to linear performance. Most of the step edge is slew limited at +8.7V/μsec where the rise time slope is giving a lower average dV/dt (7.1V/μsec) including the long tail to zero dV/dt.

Targeting a step size that should not have been slew limited by a 10% to 90% analysis, has in fact spent most of its transition in slew limiting. This might not be an issue in some applications, but a slew limited step will generally extend the settling time to a final value well beyond a non-slew limited step. That level of detail is rarely shown in simulation models, but can be seen when a measured settling time is shown on a slew limited large signal step (Figure 40, Reference 1).

If the 10% to 90% rise time line fit underestimates the true peak dV/dt, how might a non-slew limited step size be determined for an overcompensated VFA? A first pass approach would solve Eq. for VSTEP to compare the available slew rate to the t=0 dV/dt. That solves as VSTEP= SR/(F-3dB * 2π). Placing the 5.28MHz small signal response into this with the 8.7V/μsec model slew rate yields a maximum non-slew limited step size of 0.26V – far lower than the approximate 10% to 90% line fit estimate of 0.74V using Eq. 2.

This first-order step response approach is often over-conservative. All physical op amps actually have higher frequency poles that produce a t=0, dV/dt=0. If that higher frequency pole is known (32.4MHz from Fig. 3), an adjustment to the first-order analysis can be made to more accurately set the maximum step size before slew limiting will occur – or conversely target a required slew rate for a desired output step size.

A more detailed two-pole step response analysis for the peak dV/dt will yield Equation 5. The firstterms are the single pole peak dV/dt where the β expression adjusts that down for the presence of the second pole. The peak time is shown as Equation 6 where β ≡ P2/P1 (P1 is dominant closed loop pole, P2 is the second higher frequency closed loop pole in Hertz).

Equation 5
Equation 6

Fig. 3 simulates Av=+4V/V using the OPA1678 showing a P1 = 5.28MHz=F-3dB,  and P2 = 32.4MHz. Then:

P2/P1 = 32.4/5.28 = 6.14=β

tPEAK = 10.65nsec

Peak dV/dt| t=tPEAK = VSTEP*(32.78Mrad)*0.703

Solving this using the available 8.7V/μsec gives a maximum non-slew limited output step = 378mV greater than the single pole 260mV VSTEP calculated using Eq. 4. Applying that 0.703 factor to the peak dV/dt of Fig. 6 adjusts the expected peak down from 20.8V/μsec for the single pole equation 4 to 14.6V/μsec using the two pole Eq. 5 – more closely matching the simulated performance in Fig. 6.

Re-running an output step response for the circuit of Figure 5 developing a ±0.18V output swing (360mV VSTEP) using  a ±45mV input,  exporting that to generate the dV/dt curve, then zooming in on the rising edge just past 2μsec gives the smooth (non-slew limited) rising edge dV/dt plot of Figure 7.

Figure 7. Rising edge dV/dt just after 2µsec shows an early peak then a slow decay to zero.

Fig. 7 shows the expected dV/dt = 0 at t=0, and then slightly exceeds the expected peak dV/dt of 0.36V×5.28MHz×2π×0.703 = 8.4V/μsec. This simulated peak occurs very close to the expected 10.7 nsec and shows no flat region indicating a non-slew limited edge shape.  It also comes off that peak very quickly and starts to decay to zero as a linear step response should. This intentionally non-slew limited step size will physically settle to a final value much faster than the earlier VSTEP = 0.625 V slew limited step of Fig. 5. None of this detail is visible on the output time waveform – but easily shown taking the point slope of simulation or bench data. Another easy way to stay out of a slew limited step is to slow the input edge rate down to a ramp producing an output slope greater than rated SR. This is often done in the higher speed amplifier data sheets to significantly reduce settling times.

The commonly used 10% to 90% rise time is only useful as a slew rate measure if the output step spends most of its transition in slew limiting. For steps that do not, or only partially, enter slew limiting, that rise time metric far underestimates the actual peak dV/dt on the output time waveform. Form the point slope from either simulation or bench data to extract this level of detail. A safe, single pole, metric for peak dV/dt is the simple Eq. 4. For more accuracy, use the higher frequency pole and Eq. 5. Next up, Insight #15 (slew rate, part 2) will explore peak dV/dt when the output step is a second-order under-compensated small-signal response shape (complex poles) – along with an improved LSBW to slew rate estimate. The intrinsically higher slew rate current feedback amplifiers and the newer fully differential amplifiers will also be considered for their slew rates.

How does slew rate interact with small signal frequency response (part 1) references.

  1. TI OPA192, “36V, Precision, Rail-to-Rail I/O, Low Offset Voltage, Low Input Bias Current, Op Amp with eTrimTM
  2. TI OPA1678, “Dual,Low Distortion, Low Noise, Audio Op Amp”,
  3. Planet Analog article “Why is Gain Bandwidth so Confusing, Insight #12”, Michael Steffes, Sept. 23, 2019,
  4. TI THS4500, “Wideband, Low-Distortion, Fully Differential Amplifiers”,

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