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Separating linear from slew limited performance in high speed amplifiers (Part 2 of 2). The signal sped up, insight #15

Much like the precision op amps of Part 1 (Ref. 1), those op amps and fully differential amplifiers (FDAs) offering over 50 MHz bandwidths will have a wide range of slew rate (SR) specifications and reporting methodologies. Unlike the lower speed precision voltage feedback (VFA) op amp amps, most (but not all) of these faster amplifiers include slew boost mechanisms that increase the available slew rate “on demand” while operating at lower quiescent current normally. The obvious need for higher slew rates comes with the much higher small signal bandwidth (SSBW) that would fall off sharply with higher output swings without slew enhancement. The different solutions offering slew boosting, estimating peak dV/dt on a linear second-order step response, exceeding slew rate in an active filter output step, and mapping large signal bandwidth (LSBW) to slew rate will be detailed here.

Slew rate boosted designs for high speed amplifiers.
The need for some kind of more capable slew rate (SR) boosting became apparent in the early 1980’s as IC processes were delivering greater than 200 MHz SSBW, but abysmal LSBW unless excessive supply current were committed to those classical designs. The first breakthrough came with the current feedback amplifier (CFA) pioneered by Comlinear in the early 1980’s. Topologically, this amplifier operates combining an input unity gain voltage buffer from the V+ input to the V- where that inverting node shows a low impedance to what becomes a current feedback error signal (Ref. 2). Potential slew limiting shows up as an increasing inverting current into the forward transimpedance stage, slewing the compensation capacitor faster and faster as the signal demands push into higher dV/dt demands on the output signal.

Bypassing the input buffer stage by operating inverting will give the highest slew rate. In fact, the CFA input buffer slew rate can often be the overall limit for lower gain applications. The CFA is still the most capable “slew rate on demand” topology but comes with relatively poor DC precision and noise. The usual limit to slew rate in CFA devices comes with input stage saturation as the current mirrors steering the feedback error current to the compensation node show higher voltage drops. More recent developments have pushed further where it has become very difficult to even find a slew limit on the latest CFA devices. Figure 1 shows this with measured step response data converted to edge dV/dt for the recent THS3491 CFA (Ref. 3).

Figure 1. Large signal step response with point slope dV/dt zoomed in on the rising edge showing no slew limiting.

This gain of +5 V/V is not limited by the input buffer and shows no flat region in the dV/dt plots indicating a slew rate limit has not been exposed. The negative going edge is similar. Since that 15 V/nsec peak dV/dt on the 20 V step was not correlated by the 10 VPP LSBW (fig. 4, ref.3), a more conservative 8 V/nsec specification was used. This LSBW based SR specification is very typical in CFA datasheets as the step edge rates rarely slew limit in higher (or inverting) gain settings when the main CFA forward path is the theoretical limit.

The next slew boosted design, applied to higher speed voltage feedback amplifiers (VFAs), modified the classic input differential pair to two unity gain buffers driving a resistor between their outputs. The feedback error voltage is converted to an error current in that internal resistor passing on that current to a forward path that looks like a CFA internally. This brings the high slew rate benefits of CFAs with the topological familiarity of VFA – but with relatively higher input voltage noise than classic VFA. Figure 2 shows a typical internal schematic from the LT6274 (page 10, ref. 4) showing the two input buffers driving the “transconductance” element (R1) between them. While this device reports a 2200 V/μsec slew rate, that comes with a 10nV/√Hz input voltage noise for this ±15V supply op amp.

Figure 2. Internal schematic for the high slew rate, unity gain stable VFA, LT6274 showing input buffers with transconductance element.

More recently, the emerging fully differential amplifiers (FDAs) have added slew enhanced, low gain stable, VFA versions that combine low noise and DC offsets with a slew boosted input stage. The FDA has a natural output stage differential slew rate advantage doubling their two-output stage slew rates into a higher differential output SR. Their input stage slew boosting vastly improves LSBW and harmonic distortion for the single ended input to differential output configuration. Table 1 shows a range of these devices where those with slew enhancement are easily identified by their higher SR on lower quiescent current. These lower quiescent currents are always static DC numbers. All slew boosted designs increase their dynamic supply currents when their slew enhancement mechanisms are operating.

Table 1. Negative Rail In, Rail-Rail out, high speed fully differential amplifiers.

Estimating peak dV/dt on a second-order output step response.
Any of these higher speed devices will attempt to produce a linear output step response where most higher-speed amplifier designs can be approximated by a second-order shape. Only when that linear response exceeds the available slew rate will it break off into a slew limited transition. Figure 3 shows the required scale factor to estimate peak dV/dt parametric on Q for an ideal second-order step response given the small signal frequency response F-3dB and the desired output step size, VSTEP (fig. 5, ref. 5).

Figure 3. Required multiplier for peak dV/dt on a second-order response vs Q used to predict required peak dV/dt in an ideal second-order linear step response.

This exact result can be approximated by the simple Equation 1 where VSTEP is the desired final value step size excluding overshoot effects.

Eq. 1

This 2.85X multiplier only slightly overestimates the peak dV/dt in a 0.7<Q<1.5 range. This is a useful span for most simple high-speed amplifier gain stages operating with a maximally flat Butterworth (Q=.707) to a 4 dB peaked response shape (Q=1.5). Starting from a measured (or simulated) small signal frequency response (SSFR), the F-3dB and Q may be estimated with the required minimum slew rate (SR) estimated via equation 1. If the desired output step size requires more peak dV/dt than the device SR, the output step response will break off the ideal second-order linear shape and enter its peak dV/dt transition set by its SR.

Slew limited step responses in active filter designs.
The closed loop SSFR for the total applications circuit will determine the requisite peak dV/dt for an output step. One of the more common applications applying higher speed amplifiers to lower speed closed loop responses is active filters. Most design flows suggest an intrinsic gain bandwidth product (GBP) in the implementation op amp far higher than the target filter response bandwidth. This GBP margin arises from several considerations – but at a minimum aimed at reducing GBP variation from the final filter response production spread leaving only the RC tolerances (Ref. 6). Here, an example second-order low pass design will be implemented using two similar op amps with widely different slew rates. This will allow a slew limited large signal step response for the filter to be illustrated using the lower SR device.

For illustration, target the higher Q stage of an overall gain of 2 V/V, fourth-order, Butterworth filter with a 500 kHz cutoff frequency. Some active filter design tools (Burr Brown’s Filterpro here) divide the gains equally between the stages and place the highest Q stage at the output. This approach limits the input edge rates into this highest Q stage—but an ideal fast edge will be used here to illustrate the slew limiting effects. Using an initial exact RC solution for an ideal VFA op amp would deliver the expected performance metrics listed in Table 2.

Table 2. Expected SSFR parameters for the example active filter stage

These listed parameters are:

  • Required minimum GBP targeting a minimum loop gain (LG) of 20 dB (Ref. 6)
  • Desired stage DC gain. This is the total gain of 2 V/V scaled to √2 in each stage (or 3 dB).
  • Desired F0 = 500 kHz
  • Desired Q = 1.31
  • Peak frequency in the SSFR is at 421 kHz
  • Peaking for this response shape will be 3 dB
  • Peak gain adding that 3 dB to DC gain of 3 dB will be 6 dB
  • Expected SSFR F-3dB will be 695kHz–this is used in Equation 1.

To show the effect of a slew limited output step in this filter, use the two devices detailed in Table 3 where both have adequate GBP, but the LMP8671 (Ref. 7) is 1/10 the SR of the newer OPA810 (Ref. 8).

Table 3. Key parameters for two possible active filter implementation VFAs.

These two higher voltage VFAs are very similar in their modelled GBP, but the more precision oriented LMP8671 offers a relatively low SR for its GBP. To illustrate the same active filter design using each device, constrain the design by their overlapping limits in performance:

  • Use ±12 V supplies to stay within the 27 V maximum total for the OPA810
  • Target no more than a peak ±10V output swing (including overshoot) to avoid output clipping for the LMP8671 with its 1V output headroom requirement
  • Used a 5 kΩ load to stay under the maximum linear output current of 10 mA for the LMP8671 for the ±10 V peak output swing.
  • Scale the MFB resistor values up over what a lower noise design would suggest to again avoid output current limits on the LMP8671 (the MFB feedback resistor appears in parallel with the load).

The set of RC values shown in Figure 4 achieve the desired response shape using a best standard RC value fit algorithm with GBP adjustments. The SSFR shape is identical using either op amp with these RC values. The peak gain and F-3dB markers show exact fit to target.

Figure 4. Small signal response simulation showing the expected results of Table 2.

To generate an output square wave that hits a +/-10 VPEAK including overshoot effects, Equations 2 and 3 may be used to map SSFR dB peaking to percent overshoot by sweeping Q in both, then plotting percent overshoot vs. dB peaking.

Eq. 2
Eq. 3

Sweeping Q from a flat SSFR at Q=0.707 to a peaking of 7.5 dB (Q=2.3) yields the plot of Figure 5.

Figure 5. Step response overshoot vs SSFR peaking used to predict peak output vs dB peaking in SSFR.

The 3 dB peaking design of Fig. 4 should have a square wave overshoot of ≈28% on each transition. To hit a particular ±VPEAK on the ideal linear output waveform, solve Equation 4 for the required target final values in the output step.

Eq. 4

Targeting a ±10 V peak output, with a 0.28 = overshoot (OS) term, yields a targeted output final value swing of ±6.4 V. This then requires an input square wave of ±4.55V to produce the ±10V output overshoot peaks for this gain of 1.41 V/V design. Going back to Eq. 1, with a VSTEP = 2*6.4 V = 12.8 V, and an F-3dB = 695 kHz, will predict a peak dV/dt = 2.85*12.8 V*(695 kHz) = 25.3 V/μsec. This slightly exceeds the available slew rate for the LMP8671 but is well within the SR capability of the OPA810. Simulating a 50 kHz, ±4.55 V fast edge input square wave, and showing both device output steps, clearly shows the LMP8671 implementation has gone non-linear, while the OPA810 implementation remains ideal in Figure 6.

Figure 6. Large signal output step response for the two implementation op amps showing non-linearity on the slew limited LMP8671 step.

The OPA810 implementation is hitting the expected peak ±10 V swing with final values for both options settling to the desired ±6.4 V swing. While it is impossible to see here, the LMP8671 model has entered a 20 V/μsec slew limited edge rate that clips off the peak and recovers to a final value slowly. Taking the point slope for the positive transition using both op amps will give the detailed dV/dt of Figure 7.

Figure 7. Rising edge point slope using the two devices in Table 3 for the active filter of Fig. 4.

The OPA810 implementation hits the expected peak 25 V/μsec linear dV/dt from Eq. 1 (and Fig. 3) while the LMP8671, in the same RC circuit, shows its slew limited edge with a 20 V/μsec flat region.

This detailed example shows how useful Eq. 1 might be to predict the linear peak dV/dt and thereby screen to suitable VFA op amps that will support that with some SR design guardband (usually at least 1.5X).

Linking large signal bandwidth to slew rate.
From the earliest op amp days, development groups have attempted to provide a link between the device slew rate and LSBW. The most common (and erroneous) is the simple Equation 4.

Eq. 4

The LSBW is the F-3 dB using a test output level of ±VPEAK at lower frequencies swept up in frequency. Somehow this Eq. 4 became entrenched in the literature where the obvious mistake here is the actual output VPP is down -3dB at the bandwidth measurement point. As you perform a large signal swept frequency measurement on a network analyzer, the onset of slew limiting will push more power into the harmonics while the network analyzer is tracking only the fundamental power. A more accurate (but still approximate) estimate of device slew rate from LSBW measurements is the -3dB adjusted Eq. 5.

Eq. 5

The LMP8671 shows a 9 MHz, 1 Vpp, bandwidth (fig. 19, ref. 7). Using the classic Eq. 4 would predict a 28 V/μsec SR, while making the simple adjustment for the fundamental being -3 dB down in Eq. 5 yields the more accurate 20 V/μsec matching the datasheet and simulation in Fig. 7.

Since the step response edge rate for slew boosted designs often show a much higher peak dV/dt (Fig. 1) than Eq. 5 would predict, a conservative SR number is often reported from LSBW tests for higher speed, slew boosted, devices like the THS3491 (section 5, ref. 3)

There are quite a range of slew rate specification approaches applied to high speed amplifiers. Rise-time oriented approaches are the least accurate. Peak dV/dt on the edge rates are often not correlated to LSBW measurements for slew boosted designs. The safest approach appears to be a LSBW measurement mapped back to SR through some form of Eq. 5 where an added 0.8 factor is sometimes used (Ref. 9). Lower speed, and non-slew boosted like the LMP8671, devices seem to show better step edge rate correlation to Eq. 5. Consider the SR specification as very approximate and select devices with a comfortable margin to the application demands if slew limited performance needs to be avoided. Next up–details on the fine scale settling performance for high speed amplifiers.


  1. Planet Analog article “Separating linear from slew limited performance in amplifiers (Part 1 of 2).The signal sped up, insight #14”, Michael Steffes, Nov. 12, 2019,
  2. Elantec application note, “Practical Current Feedback Amplifier Design Considerations”, Barry Harvey, March 24, 1998,
  3. TI THS3491, “900 MHz, 500 mA High Power Output Current Feedback Amplifier”,
  4. LTC LT6274, “90 MHz, 2200 V/μsec, 30 V Low Power Op Amps”,
  5. EDN article, “What is op amp slew rate in a slew enhanced world, part 1”, Michael Steffes, Jan. 8, 2017,–Part-1
  6. Planet Analog article “Use true gain-bandwidth product to estimate required margin in active filters. The signal sped up, insight #13”, Michael Steffes, Oct. 18, 2019,
  7. NSM LMP8671, “40 V Low Noise Precision Amplifier”,
  8. TI OPA810, “140 MHz, Rail to Rail I/O, FET Input Op Amp”,
  9. TI application note, “Large Signal Specifications for High Voltage Line Drivers”, Kristoffer Flores, Xavier Ramus, June 2011,


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