Serdes about to get extreme makeover

SAN FRANCISCO, Calif. — Serdes, the serializer/deserializer chips at the heart of many high-speed designs for the past decade, are about to get an extreme makeover. The devices will shift from analog to digital techniques for many designs over the next few years, according to a panel of experts at the International Solid State Circuits Conference (ISSCC).

Just how and when that transition will take place was a matter of debate for five panelists. They argued whether analog-digital converters (ADCs) would replace binary front-ends for serdes in backplane-based computer and communications systems.

“My answer is absolutely yes,” said Ichiro Fujimori, a director of analog engineering at Broadcom. “At data rates of 20 Gbits/s and beyond ADCs will become mainstream,” he said.

Fujimori said ADCs combined with multi-level coding techniques will enable lower cost designs, following the pattern set by DSL and voice-band modems years ago.

“It's an interesting time for serdes designers,” he said. “Our analog and digital teams are starting to work much closer together.”

Hirotaka Tamura, a researcher at Fujitsu Labs Ltd., agreed. He argued that a design using a 3-bit ADC and a suitably optimized analog front end can support tomorrow's data rates with similar cost and die size as today's designs.

“CMOS technology trends are in favor of ADCs,” he said.

Engineers from Texas Instruments and IBM took a more measured view, suggesting different designs will use a fragmented set of new techniques.

“There is an inevitable trend toward ADCs at higher data rates where [long reach] channels are fixed and use non-return to zero signaling,” said Andrew Joy, a distinguished member of technical staff at TI. But short reach designs will stay with current techniques for awhile and “in the long term, if we want to get the best performance from a channel, we have to go away from serdes and ADCs,” he said.

“It's not as easy as in the DSL days because we are right at the performance limit of the technology,” he added.

Michael Sorna, a member of technical staff at IBM, agreed. He noted that serdes are used for a wide range of designs beyond backplanes, including long distance optical and copper links and chip-to-chip interconnects.

What designers use in the future “depends on the target appplication,” Sorna said. “Today's 10G backplanes are well suited to analog equalization, but the question is where the power is going long term,” he said.

“My position is there is no one-size-fits-all solution,” said Jared Zerbe, a technical director at Rambus. “There are many variables, and ADCs and advanced [analog] line-rate equalization are not that different when you boil them down,” he said.

“ADCs are not and will never be a panacea,” he added. “They are too expensive for slow links and too slow for fast links, but they are a best fit for medium speed and very complex backplanes, especially if Moore's Law stays ahead of data rate requirements,” he said.

The debate comes on the heels of discussions at DesignCon about looming issues in testing systems at 20 Gbits/s and beyond. One panel of experts said they foresee serial data rates as high as 25 Gbits/s on the horizon.

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