AnalogX has made available the 6 nm and 7 nm SerDes intellectual property (IP) for chiplets and chip interconnects serving designs in artificial intelligence (AI) and data center environments. According to the company, the focus for this chip-to-chip and die-to-die interconnect IP is on low power and latency.
Nearly a year after Inphi and MediaTek’s ASIC services unit unveiled 7 nm SerDes IPs for data center and other high-speed communication designs, AnalogX has announced a silicon-proven solution for 7 nm as well as 6 nm process nodes.
Figure 1 AXLinkIO IPs support a multitude of serial standards for system-on-chip (SoC) and chiplet links. Source: AnalogX
Kandou is another SerDes IP supplier that has recently provided its chip-to-chip link technology for Coherent Logix’s programmable processors for embedded systems. Kandou’s Glasswing SerDes IP—based on its CNRZ-5 Chord signaling architecture—simplifies the integration of multiple chips in a single package.
Also, in October 2020, AnalogX announced the outcome of its collaboration with OpenFive, a self-contained and autonomous custom silicon business unit of SiFive, for developing a chip-to-chip interface subsystem optimized for AI, high-performance computing (HPC), networking, storage, aerospace, and 5G base station applications. The collaboration combined OpenFive’s Interlaken Controller IP, which supports from 1 up to 48 SerDes lanes with up to 112 Gbps data rates, with AnalogX’s ultra-low-power SerDes IP AXLinkIO.
Figure 2 The chip-to-chip mesh fabric is based on OpenFive’s Interlaken and AnalogX’s AXLinkIO SerDes IPs. Source: OpenFive
The Toronto, Canada-based AnalogX calls 2020 a great year for the mixed-signal IP business. The supplier of low-power connectivity IP solutions has recently moved to a bigger office in Toronto and is currently hiring design engineers. AnalogX has also opened a sales office in Silicon Valley.
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