Editor’s note : I am pleased to bring you another of Texas Instrument’s on-going Signal Chain Basics tech blogs with #114. This month we are happy to have author Luis Chioye, Applications Engineer, Precision Analog
When designing circuits with precision analog-to-digital converters (ADCs), designers must carefully consider all sources of noise in the acquisition system, including noise injected through the power supplies. Many of today’s compact modules in industrial systems, portables and battery-powered equipment incorporate DC/DC switching regulators, capable of producing rail supplies with high efficiency at the expense of supply ripple. It is important to understand the effects of supply ripple and reduce supply noise to ensure the optimal performance of the successive approximation register (SAR) acquisition system.
Let us define the parameters used to measure the effects of power-supply variation on the SAR ADC. Power supply rejection ratio (PSRR) is a measure of how immune the ADC transfer function is to changes in the applied power supply voltages. PSRRDC refers to the ratio of change in full-scale gain or offset when applying a DC or static change in the power supply voltage:
PSRRAC is the ratio of the output spectral power with respect to the injected AC signal power on the supply pin displayed on a fast Fourier transform (FFT) plot.
Figure 1 illustrates the FFT plot measuring PSRRAC for a given supply ripple frequency.
FFT plot of PSRRAC measurement.
Switching regulators provide a compact solution to generate voltage supplies with high efficiency over a wide set of input voltage and current load conditions. However, their efficiency comes at the expense of switching ripple, with frequencies ranging from 10s of kHz to a few MHz. When designing with precision SAR ADCs, designers must account for the effect of the DC/DC supply ripple on the ADC, as well as the effect on other components in the signal chain, such as the amplifier driver and reference driver circuits in the acquisition system. SAR ADCs generally offer good PSRR over-frequency to ranges up to 100s of kHz. However, SAR ADCs (and driver amplifiers) may show PSRR degradation as the ripple frequency increases (Figure 2 ).
PSRR versus power-supply ripple frequency for a typical SAR ADC.
Estimating the effects of ripple on a SAR system
For illustrative purposes, consider the SAR ADC acquisition system in Figure 3 .
SAR ADC acquisition system.
The 5.2 V analog supply (VA) provides power to the SAR ADC, driver amplifier and reference driver circuits. To estimate the effect of supply ripple in the entire system, the effect at each circuit component is calculated using the device PSRRAC specification.
Consider the supply ripple of a particular DC/DC converter with a fixed load of PSRRAC 15 mA (Figure 4 ).
Regulator output ripple.
The supply ripple in Figure 4 has 21 mVp-p of amplitude, and a frequency of ∼70 kHz, which produces additional harmonics at multiples of this frequency.
Using the amplitude, fundamental frequency and PSRRAC specifications, the output ripple spur for each circuit component is estimated in Table 1 :
Estimate of output ripple on each circuit component.
Performing the root-sum-square (RSS) of the circuit component’s output ripple provides an estimate of the output spur at ∼70 kHz for the entire circuit:
Since the full-scale range is 4.096 V, the magnitude of the spur is calculated in dBFS:
Spurious-free dynamic range (SFDR) is a dynamic or AC figure of merit that measures the ADC’s capability to resolve a signal from other noise or spurious components. For example, the expected SFDR performance of the ADS8331 is 98 dB. Therefore, per equation (5), the spurs due to the supply ripple degrade system performance.
There are several methods to filter the ripple including solutions implementing passive LC filters and power filters. However, a solution that provides low noise and good DC stability is to select a low dropout regulator (LDO) with high supply ripple rejection over an extended frequency range. For instance, the TPS7A4901 offers high PSRR (≥52 dB) over a wide frequency range (up to 400 kHz) and very low output noise (15.4 μ VRMS ). Figure 5 shows the measured FFT performance of the ADS8331 acquisition system when powered by the DC/DC switch regulator directly, and while using the DC/DC regulator is cascaded with the LDO (TPS7A4901) to filter the ripple supply noise.
Measured performance with DC/DC regulator versus a DC/DC regulator + LDO.
The results in Figure 5 show the supply ripple effect on the performance of the SAR ADC acquisition system. The FFT shows supply ripple spurs at multiples of ∼ 70 kHz, and additional tones produced when the DC/DC supply ripple is modulated with the 10 kHz input signal appearing at 10 kHz +/- 70 kHz. In addition to good printed circuit board (PCB) layout and supply decoupling practices, filtering the supply ripple with an LDO offering high PSRR over the frequency range of the supply noise provides an effective method to eliminate supply ripple.
Join us next time when we discuss current feedback amplifiers and the impact of transimpedance on bandwidth, gain and slew rate.