Editor’s note: I am pleased to bring you the next edition of TI’s Signal Chain Basics, authored by one of the most talented RF/High Speed Systems guys with whom I have ever worked—Robert Keller. Enjoy.
As analog-to-digital converters (ADCs) increase in sample rate and input frequency, applications such as wireless and wireline communications, electronic warfare and radar have rapidly consumed all advances with new system needs. This will continue in the future – for example new communication standards like 802.11ad and 5G cellular will use multiple GHz of bandwidth and require sample rates of up to 10 GSPS. At the same time, these standards will still require high dynamic range in order to observe small signals with sufficient clarity. One technology for addressing these needs is time-interleaved ADCs.
For high-speed ADCs, there is a tradeoff between performance, sample rate and power. Time interleave uses multiple ADCs sampling at different times to increase the effective sample rate, while providing the performance of a slower sample rate ADC. This comes at the expense of needing double the power, but often this is lower than the power needed to achieve double the sample rate with a single ADC.
Figure 1 shows an example of two ADCs interleaved to double the sample rate. A clock with two phases, 0 and 180 degrees, is used for each ADC so that two samples are provided for each clock cycle.
Time-interleaving of two ADCs.
While the example in Figure 1 shows time-interleaving of two ADCs, it is possible to interleave many more ADCs – one recent paper describes interleaving 32 ADCs .
However, one challenge with time-interleaving ADCs is that mismatches in offset, gain and timing cause artifacts that degrade signal quality. For example, a four-way time-interleaved ADC will generate the artifacts in Table 1 for an input signal at frequency IF.
Mismatch and artifacts for a four-way time-interleaved ADC.
There are three common ways to mitigate these effects: calibration, correction and dithering.
Calibration uses a known signal such as a voltage ramp to measure the mismatches and adjust the ADC accordingly. The ADC is not digitizing the signal during the calibration time. Therefore, an extra ADC core is often used to allow offline calibration during normal operation. Then the calibrated core is swapped for another core to be calibrated. For example, this technique is used on the ADC12J4000, 12-bit 4-GSPS ADC, which has five cores with four used in normal operation.
Correction uses the signal itself to estimate and correct the mismatches. The compensation can be done in analog or in the digital domain, or both. For example, to adjust the timing mismatch, the ADC clock can be delayed (analog compensation) or by adjusting a digital filter that can be varied to product slight variations in the signal latency.
Similar to calibration, dithering uses an extra ADC core that is randomly swapped with other ADC cores in operation. In this way, the effects of mismatch are whitened, or spread across the spectrum, essentially converting the artifact energy into noise. As dithering does not remove the artifact energy, it is important that the mismatches are small so that the noise of the ADC is not significantly increased.
These techniques can be and are often used together. Table 2 lists the advantages and disadvantages of each technique.
A comparison of the pros and cons of time-interleaving mismatches.
Figure 2 shows the output spectrum of the ADC32RF45 (a 14-bit, 3-GSPS ADC) for an input tone of 1.804 GHz sampled at 3-GSPS with and without interleaving correction. The interleaving artifacts are improved by at least 30 dB to better than 80 dBFS, lower than the second- and third-order harmonics (labeled HD2 and HD3).
Output spectra with and without interleaving correction.
Time-interleaving is an increasingly popular way to increase sample rate with better performance and lower power; techniques for mitigating the artifacts can provide a high dynamic range.
Stay tuned for the next Signal Chain Basics article with advice on working with data converters, amplifiers, interface or other analog design challenges.
- Frans, Yohan, et al. “A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET,” IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016.
- For more information about high-speed data converters, click here.
- Here’s more information about clocks: click here.
About the author
Robert Keller is a Systems Manager in TI’s High-Speed Products group. He has 15 years of experience supporting high-speed products in wireless infrastructure communication, test and measurement and military systems. He received a B.A. in Physics and Mathematics from Washington University, St. Louis, Missouri, and a Ph.D. in Applied Physics from Stanford University. He has 10 US patents in networking and sensor applications. Robert can be reached at firstname.lastname@example.org.