(Editor's note : go to https://m.eet.com/images/common/planetanalog/2010/02/SCBlist.pdf for a complete, linked list of all previous installments of the Signal Chain Basics series.)
There is a well-known relationship in analog-to-digital converters (ADCs) between the sample clock jitter and the resulting ADC signal-to-noise ratio (SNR) degradation (derived in reference 1), Equation 1 :
SNRjitter (dBc) = 20 * log10 (2 * p * fIN * tj )
where tj is the RMS jitter (typically in picoseconds or femtoseconds), fIN is the analog input frequency, and SNR jitter is the ADC SNR, if the only noise source is clock jitter. The total ADC SNR includes other noise sources such as thermal noise.
Here are some interesting points regarding Equation 1. First, there is no direct dependence on sample frequency. However, the integration of phase-noise to calculate jitter depends on the sample frequency. Also, since the RMS jitter value is the integrated phase-noise across frequency, the phase-noise dependence frequency dependence is lost in the analysis.
Using the RMS jitter effectively averages the phase-noise across the entire ADC output bandwidth, regardless of the actual phase-noise spectrum. Since the clock phase-noise typically decreases with increasing offset frequency, the noise due to clock jitter is highest near the large signal frequency.
This is the case when a band-pass filter is used on the clock signal, as described in Reference 2 , where a crystal filter removes the clock phase-noise above ~100 kHz. This is illustrated in Figure 1 , when the phase-noise is integrated in the wanted signal bandwidth, the noise estimated using jitter results in a higher estimate than integrating the in-band phase-noise.
Figure 1: ADC spectrum for a large blocker and small wanted signal.
(Click on image to enlarge)
How do you translate clock phase-noise to the ADC output noise? To demonstrate the relationship, we create a known level of phase-noise and measure the ADC output spectra. A 250-MHz clock with noise is generated using a high-speed DAC, such as the DAC5681 16-bit/1Gsps, and input as a clock for the ADC, using the ADS4149 14-bit/250Msps. The DAC pattern and capture size are set so the bin resolution in the DAC and ADC FFT’s are equal in size.
The DAC output pattern in Figure 2 consists of a 250-MHz tone and –60 dBc of random noise from 240 to 250-MHz. In a typical clock, the phase-noise is symmetric around the clock, but for clarity we use a single-sided noise.
Figure 2: 250-MHz clock with –60dB noise.
(Click on image to enlarge)
The ADC output using the DAC generated clock for input frequencies of 10 and 100MHz is shown in Figure 3 . The clock phase-noise energy is mixed in the sample process with the input tone and is symmetrical around the carrier. For the 100-MHz input tone, the noise due to the clock phase-noise is ~71dB across ±10 MHz from the tone. For the 10-MHz input tone, the noise due to the clock phase-noise is ~91dB (per FFT bin). This is consistent with the SNR jitter equation, which predicts a 20-dB change with 10 times the input frequency.
The ADC noise from the clock phase-noise can be described by Equation 2 :
ADCNoise (fOFFSET ) = – Phase-noise(fOFFSET ) – 20 * log10 (fIN /fCLK )
where fOFFSET is the offset frequency, phase-noise is the one-sided phase-noise density, fIN is the input frequency, and fCLK is the clock frequency. Note that the units of phase-noise and ADCNoise are the same, i.e., dBc/Hz.
Returning to our example in Figure 3, the ADC noise at 100MHz of –71dB is 11dB lower than clock phase-noise of 60dB, –8dB is from the fIN /fCLK term in Equation 2, and 3dB is due to the clock phase-noise being on one side only, rather than symmetrical.
When used for specifying the required phase-noise for the ADC clock in communication systems, the ADCNoise should be integrated across the bandwidth of the wanted signal at the blocker offset to calculate the total that falls in the wanted signal (Figure 1).
The ADC clock phase-noise spectrum translates directly to noise in the ADC output with the same offset spectrum. Therefore, using jitter to calculate SNR is a simplification that often results in over specification of ADC clock phase-noise requirements.
Join us next month when we will discuss clock jitter specifications in high speed serial data links.
1. “Clocking high-speed data converters,” b y Eduardo Bartolome, Vineet Mishra, Goutam Dutta, and David Smith, Texas Instruments, 1Q 2005.
2. “Implementing a CDC7005 Low Jitter Clock Solution for High-Speed High IF ADC Devices,” by Russell Hoppenstein and Firoj Kabir, Texas Instruments, December 2004.
About the Author
Robert Keller is the Systems and Applications Manager for High-Speed Data Converters. He has nine years experience supporting high-speed products in wireless infrastructure communication, test and measurement, and military systems. In 1988 he received a B.A. in Physics and Mathematics from Washington University in St. Louis, and a Ph. D. in Applied Physics from Stanford University in 1993. He has 10 US patents in networking and sensor applications. Robert can be reached at .