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SIGNAL CHAIN BASICS #46: Basics of clock jitter specifications in high-speed links (Part I)

(Editor's note : click here for a complete, linked list of all previous installments of the Signal Chain Basics series.)

Signal Chain Basics #41, Clock Jitter Demystified, helped you to gain an understanding of the basics of clock jitter. This two-part article deals with the basics of the impact of clock jitter on high-speed links. This article, Part 1 , provides the foundational concepts of high-speed communications links. Part 2 will address the communications link budget from a clock jitter perspective. 

Clock jitter specifications that pertain to high-speed communications links are a confusing mixture of terminology and numerical values. In order to decipher these specifications, a basic understanding of communications link architectures and clocking mechanisms is essential. The purpose of any communications link is to convey data across a transmission media with acceptable performance. Typical link performance parameters for any given media/communications environment includes data rate, transmission distance, and bit error ratio (BER).

Figure 1 shows a basic communications link comprising a transmitter, a medium of data propagation, and a receiver. The receiver includes a signal threshold to differentiate between a ‘1’ and a ‘0’ and a clocking mechanism, so that the time slot that each individual symbol occupies is identifiable.   


Figure 1: Basic serial communications link
(Click on image to enlarge)

High-speed links commonly use a serializer/deserializer (SerDes) (Figure 2 ).  The serializer multiplies the frequency presented on the transmit clock (TX CLK) port using an internal phase-locked loop (PLL). For clock recovery to separate the embedded clock from random data, the receiver must encounter a minimum density of edges; which necessitates schemes like 8B10B coding or data scrambling.


Figure 2: High-speed link – embedded clock
(Click on image to enlarge)

As the data traverses the media, discontinuities cause reflections, and cross-talk injects noise. The typical frequency response of a long transmission line is low pass, which causes problems in a system that relies on the timing of high-frequency signal content (edges). Additionally, the TX CLK oscillator injects noise into the system. Many modern communications links must achieve at least10-12 BER (for every 1012 bits received, the receiver misidentifies only one of them).

An embedded clocking application has several jitter entry points (Figure 3 ). With respect to clocking, the SerDes multiplies the reference clock so that the link achieves the desired data rate. For example, a SerDes uses a 78.125 MHz clock to generate a 3.125 GHz link; therefore, the SerDes PLL multiplies the reference oscillator by 40 to attain the internal clock required. The phase noise of the transmitter clock (TX CLK) oscillator and the characteristics of the transmitter PLL (TX PLL) play a big role in clock jitter budgeting.


Figure 3: High-speed link – jitter entry points
(Click on image to enlarge)

This is because the TX PLL passes certain noise components from the TX CLK oscillator onto the data stream, and the noise contribution of the TX PLL feedback divider is proportional to the square of its multiplication factor (e.g., 402 = 1600). 

Transmitter
The frequency response of a PLL is low pass. If the TX PLL loop bandwidth is f2, then noise above this frequency is passed through to the transmission media along with the in-band noise that is dominated by the TX CLK phase noise. 

Receiver

The RX jitter responserepresents the bandwidth of the random noise passed by the TX CLK through the TX PLL and transmission medium. The loop bandwidth of the receiver clock recovery PLL (CR) is f1 (RX PLL BW). Therefore, the RX jitter BW represents the frequency band between the bandwidths of the TX and RX PLL. For example, the jitter measurement for SONET OC48 is 12 kHz – 20 MHz. From a clocking perspective, this area has the greatest impact on link performance bit-error-rate (BER), and often is dominated by the TX CLK noise content. This jitter measurement bandwidth is an integral part of the specifications for many communications standards including SONET, SDH, and fiber channel. 

Link Budget
The transmission line contributes deterministic jitter only. All other elements comprising the communications link contribute both random and deterministic jitter to the overall jitter budget. In theory, the total budget must stay below one unit interval (1 UI) for reliable communication. 

When Part 2 is published, it will address the overall link jitter budget for a high-speed communications system and provide specific examples of link budget calculations.

Joint us next month when we will talk about the life expectancy of digital capacitive isolators.

About the Author

John Johnson is the Manager of Market Development and Systems Engineering for the Clocks and Timing Group of Texas Instruments. John has 30 years of experience in the electronics industry and has worked in the fields of product development, marketing, systems engineering, and business management. He holds a MSEE from Purdue University.

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