(Editor's note : Signal Chain Basics is an ongoing (and popular) series; you can click here for a complete, linked list of all previous installments of the series.)
Today’s high-speed digital-to-analog converters (DACs) often include digital signal processing blocks that make them much easier to use. For this discussion, we used TI’s DAC34H84 (Reference 1 ), a 4-channel, 16-bit, 1250 Msps DAC, as it is typical of these types of devices and includes an input FIFO to separate the input and DAC clock domains, digital blocks for interpolation, digital quadrature modulation with fine frequency resolution, analog quadrature modulator correction, and sin(x)/x correction (Figure 1 ). This article explains the function and value of each of these features.
Figure 1: Functional bock diagram of the DAC34H84.
(Click on image to enlarge)
The first digital block is interpolation, which increases the sample rate of the digital signal inside the DAC. Interpolation typically is done in steps of a two times increase in sample rate. It is accomplished by inserting zeros between the input sample points, which creates two signals at fIF and FIN – fIF . Passing through a digital low-pass filter removes the second signal at FIN – fIF , leaving only the signal at fIF .
The motivation for using interpolation is related to the zero-order hold output structure used in most high-speed DACs. With a zero-order hold, the DAC sets the output amplitude corresponding to the digital sample at the beginning of the clock cycle and holds it until the end of the clock cycle and the next output sample. This results in a “stair-step” output with frequency response that follows in Equation 1 :
Sin ( p × fIF /fs )/(? p × fIF /fs )
where fIF is the analog output frequency and fs is the sample rate. This response has a low-pass effect (Figure 2 ), with ~3.5 dB loss at f = fs /2 and goes to zero at multiples of fs . Although the DAC output will have images of the signal at N × fs ± fIF , the amplitude of the images in the higher Nyquist zones is significantly lower than the signal at fIF and, therefore, has lower signal-to-noise-ratio (SNR) and potentially a significant amplitude droop.
This limits most applications to output signal frequencies less than fs /2. Additionally, the separation between the signal at fIF and the image at fs – fIF reduces as fIF approaches fs /2, making an analog filter at the DAC output to remove the unwanted image at fs – fIF difficult to build, which limits fIF for most applications to less than fs /3.
Figure 2: DAC output spectrum with no interpolation.
Using interpolation in the DAC to increase the sample rate inside the DAC, the digital interface rate, fIN , to the DAC only needs to be high enough to allow transfer of the signal bandwidth, plus a small amount of additional bandwidth to allow for the interpolation filter transition band (fin > 2.5 × BW for a real signal and fin > 1.25 × BW for a complex signal). Increasing the sample rate with interpolation then places the signal comfortably below fs /2.
Another benefit of increasing the sample rate is to allow digital mixing to increase the output IF to a higher frequency. For example, with 2× interpolation, the output frequency can be placed above fin /2, which would not be possible without interpolation (Figure 3 ). Typically a complex input signal is used with a complex mixer to avoid generating images in the mixing process. The mixing output can either be a real IF signal or complex IF signal, useful when following the DAC with an analog IQ modulator.
Figure 3: DAC output spectrum with 2x interpolation.
Using a complex DAC output with an analog quadrature modulator (AQM) highlights another useful digital feature common in high-speed DACs – the quadrature modulator correction block. This block corrects for the gain, phase and offset imbalance of the analog quadrature modulator, improving the AQM sideband suppression and LO feedthrough.
Finally, at the end of the digital signal chain is a digital FIR filter to compensate for the sin(x)/x rolloff across the first Nyquist zone. In the DAC34H84 implementation, the filter compensates up to 0.4 × fDAC with less than 0.03dB of error.
As we have seen in this article, there are a lot of digital features included in high-speed DACs like the DAC34H84. These features ease system implementation by reducing data rates and improving output signal characteristics.
Please join us next month when we will examine the relationship between random jitter and phase noise.
1. “Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC),” DAC34H84 datasheet, LIT# SLAS751A, June 2011.
2. For more information about DACs from TI, visit: www.ti.com/dac-ca.
About the Author
Robert Keller is the Systems and Applications Manager for High-Speed Data Converters. He has nine years experience supporting high-speed products in wireless infrastructure communication, test and measurement, and military systems. He received a B.A. in Physics and Mathematics from Washington University, St. Louis, and a Ph.D. in Applied Physics from Stanford University. He has 10 US patents in networking and sensor applications. Robert can be reached at .
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