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SIGNAL CHAIN BASICS #67: How to design a two-to-four wire converter for RS-485

( Editor's note: Signal Chain Basics is an ongoing and popular series; click here for a complete, linked list of all installments.)

Multipoint data communication networks such as Profibus, Modbus, and BACnet often require interoperability of RS-485 two-wire, half-duplex and four-wire, full-duplex bus systems.

These systems can extend to several hundreds of meters and are subject to large ground potential differences (GPD). These potential differences can exceed the common-mode voltage range of a transceiver and damage the device.

To eliminate GPDs, galvanic isolated transceivers are used to separate a bus node’s control electronics from the actual transceiver stage connected to the bus.

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(Editor's note : Signal Chain Basics is an ongoing and popular series; click here for a complete, linked list of all installments.)

In Signal Chain Basics #60 (Reference 1 ), we discussed approaches for tracking down spurious signals in high-speed analog-to-digital converter (ADC) systems. In this article, we examine similar techniques for high-speed digital-to-analog converter (DAC) systems.

There are two types of high-speed DACs: interpolating and non-interpolating (straight). Interpolating DACs, described in Signal Chain Basics #55 (Reference 2 ), typically contain digital signal processing features such as interpolation, digital quadrature modulation, and internal phase-locked loops (PLLs). Straight DACs simply convert digital values to an analog output.

Figure 1 shows a DAC signal chain in a radio application. There are several potential sources of spurious signals from the DAC, each has distinct characteristics:

1) Digital interface

2) Input clock

3) PLL

4) Power supplies

5) Digital saturation

6) Improper output termination

 

Figure 1 : Typical high-speed DAC signal chain.

(Click here to enlarge image)

DACs are characterized with both a continuous wave (CW) or modulated signal output (commonly a 3G or 4G communication signal like WCDMA or LTE). Datasheets contain AC specifications listed in a table as well as output spectral plots. Comparing against the spectral plots offers the most information for debugging system problems, as each problem type has different frequency characteristics.

To debug a high-speed DAC, first verify error-free data input. Input interface problems are common and cause bit errors, resulting in wideband noise. In a straight DAC this causes an elevated noise floor following a sin(x)/x frequency response (Figure 2 ). In an interpolating DAC, the noise spectrum is shaped by the internal digital interpolation filters. This gives a distinctive output spectrum that matches the filter frequency response (Figure 3 ).

 

Figure 2 : Output spectrum for a straight DAC with interface errors.

(Click here to enlarge image)

 

 

Figure 3 : Output spectrum for an interpolating DAC with interface errors.

(Click here to enlarge image)

DACs such as TI’s DAC34SH84 (quad-channel, 16-bit, 1.5 GSPS) include several features for easing design, validating and monitoring the input interface. The DAC includes a programmable skew between clock and data with ~50 ps increments to reduce input timing requirements. To validate, a test pattern from the digital source can be used to identify specific error bits. Finally, the interface includes a parity bit for continuous interface monitoring during operation.

Clock spurs are another common source of problems. Because the DAC sampling process acts like a mixer, spurs on the clock input result in spurs at the DAC output. The frequency of spurious signals at the DAC output due to clock spurs move 1:1 with input frequency.

This is easiest to see by generating a tone, recording the spur’s frequency, shifting the tone by a small amount (for example, 100 kHz), then measuring the frequency shift. Switching regulators can cause clock spurs offset from the tone by a few 100 kHz.

Another common clock problem is improperly setting the internal PLL, resulting in either unlocked PLL or elevated phase noise.

Non-linear distortion generates output signal harmonics. Due to the DAC’s sampling nature, harmonics generated at frequencies above the first Nyquist zone (0 – fSAMPLE /2) fold back into the Nyquist zone at the DAC output. While the spur’s frequency can be easily calculated, you can identify the harmonic by observing the change between output and input frequencies. Harmonics change in output frequency by:

??fOUT = ±N × ?fIN

where ?fIN is the change in input frequency, N is the harmonic order, and ?fOUT is the change in output frequency.

Two common causes of non-linear distortion are digital saturation and improper output termination. Interpolating DACs often have signal processing blocks with potential gain, causing signal clipping. Clipping generates a large number of harmonics (Figure 4 ).

 

Figure 4 : DAC output spectrum with digital saturation.

(Click here to enlarge image)

In high-speed DACs, the output current is converted to voltage by the termination load. The datasheet contains specifications for output compliance voltage, which is the acceptable voltage range at the DAC output pins. Exceeding the compliance voltage specification, which can occur if the output-load impedance is too high, increases distortion. Note that the impedance may be frequency-dependent, if for example it includes an analog filter and the critical impedance is at the expected operating frequencies.

This is not a complete list of potential problems, but most issues found when debugging high-speed DAC systems fall into one of these categories. The key is to track down the source by identifying the spurious signals’ characteristics.

Please join us next month when we explain the basics of level-shifting when interfacing two components operating at different supply voltages.

References

  1. Keller, Robert. SIGNAL CHAIN BASICS #60: Tracking down spurious signals in high-speed ADCs, EETimes/Planet Analog, December 12, 2011.
  2. Keller, Robert. SIGNAL CHAIN BASICS #55: Digital features in high-speed digital-to-analog converters, EETimes/Planet Analog, July 17, 2011.
  3. For more information on high speed DACS, visit: www.ti.com/dac-ca.

About the Author

Robert Keller is the Systems and Applications Manager for High-Speed Data Converters. He has nine years experience supporting high-speed products in wireless infrastructure communication, test and measurement, and military systems. He received a B.A. in Physics and Mathematics from Washington University, St. Louis, and a Ph.D. in Applied Physics from Stanford University. He has 10 US patents in networking and sensor applications. Robert can be reached at . 


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