Advertisement

Article

SIGNAL CHAIN BASICS #71: How supply noise impacts clocking devices

Introduction

Supply noise can degrade the random jitter performance of clocking devices. Random jitter is calculated from phase noise (L), offset frequency (f), and clock frequency (Fclk) (Equation 1):
      
        


Click on image to enlarge.

 Equation 1

Typically, L(f) is the clock’s phase noise, but also could mean the spurs and phase noise on the clock as a result of supply noise. It is the noise and spurs near the clock frequency that cause jitter degradation. For instance, if there is 10 kHz supply noise onto a 100 MHz clock, it is not 10 kHz spurs, but rather the spurs at 100 MHz +/– 10 kHz that cause jitter degradation.

To understand supply noise impact in general, first examine the impact of a sinusoidal noise source using Equation 2:

    


Click on image to enlarge.

 Equation 2
      
Once the impact of this supply noise is understood for an arbitrary frequency, f, this can be expanded to any spectrum of power supply noise. By understanding how the noise source (Equation 2) impacts a clocking device’s most noise-sensitive blocks, and how they are shaped by the phase-locked loop (PLL), the resulting impact on jitter can be found.
      
Supply noise impact on an oscillator

Oscillators such as VCOs, VCXOs, XOs, OCXOs, and TCXOs can be considered for the purpose of supply noise discussions. Their supply noise sensitivity can be characterized with the supply pushing constant, KPUSH , as the frequency for a given change in supply voltage.

The noise source in Equation 2 produces sidebands at frequencies equal to Fclk +/– f. The amplitude of these sidebands can be calculated using Equation 3.
   


Click on image to enlarge.

 Equation 3
    
ß is the modulation index and calculated by traditional FM modulation theory (Equation 4).


Click on image to enlarge.

Equation 4

Depending on whether the oscillator is free-running, driving a PLL, or being driven by a PLL, the noise response differs (Figure 1).


Click on image to enlarge.


Figure 1. Oscillator’s supply noise response in a PLL system.

Figure 1 shows that low-frequency supply noise has the most severe impact on oscillator phase noise. If the oscillator is locked to a PLL, then increasing the loop bandwidth helps suppress this low-frequency noise. If the oscillator is used as a reference, reducing the loop bandwidth can help reduce high-frequency noise. In either case, better supply filtering, especially at low frequencies, is critical. Truly low noise low drop-out (LDO) regulators are good for this purpose.

Supply noise impact on other blocks of the clocking device

For blocks other than the oscillator, supply noise response tends to be more flat over frequency (before shaping from the PLL). One way that supply noise can impact the clocking device is at the charge pump supply pin and noise response (Figure 2).


Click on image to enlarge.

Figure 2. Supply noise shapes impact on PLL noise.

For the output buffer, the supply noise can come through the power supply pins and pull-up or pull-down resistors (like LVPECL emitter resistors). With multiple outputs of different frequencies, bypass capacitors are not always helpful because noise generated by one output supply pin can couple onto another pin through these capacitors.

Example

Figure 3 was created by first measuring the supply noise impact for a 25 mV signal with a very narrow bandwidth to extrapolate a pushing constant of 650 kHz/V. Next we used a wide-loop bandwidth to measure just the PLL charge pump. Finally, we used a loop bandwidth of about 50 kHz to combine these results.


Click on image to enlarge.

Figure 3. Measured impact of supply noise on a PLL and VCO system.

Relating spurs to jitter

Now that we calculated the spurs created by a fixed frequency, Table 1 uses Equation 1 to translate these spurs to jitter.
 

Clock Frequency

10 MHz

20 MHz

50 MHz

100 MHz

Spur

-30 dBc

711

356

142

71

-40 dBc

225

113

45

23

-50 dBc

71.2

35.6

14.2

7.1

-60 dBc

22.5

11.3

4.5

2.3

-70 dBc

7.1

3.6

1.4

0.71

-80 dBc

2.3

1.1

0.45

0.23

-90 dBc

0.71

0.36

0.14

0.07

Table 1. Relating spurs to jitter in ps.

Summary

By understanding how supply noise of arbitrary frequency can impact each block of a clocking device, the induced jitter can be found for any jitter integration bandwidth, device configuration, or supply noise spectrum.

References

For more information about clocks and timers from TI, visit: www.ti.com/clocksandtimers-ca.

About the author

Dean Banerjee is an applications engineer for TI’s Signal and Data Path Solutions Business Unit. He has been involved with phase-locked loop (PLL) frequency synthesizers for over 15 years, and authored a book: “PLL Performance, Simulation, and Design.” He holds a master’s degree in applied mathematics from the University of Illinois, and an MSEE degree from Southern Illinois University.

Past Signal Chain Basics in the series are here.

0 comments on “SIGNAL CHAIN BASICS #71: How supply noise impacts clocking devices

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.