Signal Chain Basics #74: Band-Limited Dither Improves SFDR in High-Speed DACs

High-speed digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) have different distortion properties than other analog components. The more purely analog components such as amplifiers are ideally linear and saturate smoothly. But DACs and ADCs can exhibit abrupt steps in their transfer functions. As a result, they don't exhibit the predictable and dominant second- and third-order harmonic distortion (HD2 and HD3).

The commonly used architectures for high-speed DACs and ADCs, such as current steering DACs and pipeline ADCs, both rely on component matching between high- and low-resolution bits in their architectures, and non-ideal matching produces abrupt steps in the input/output transfer function. This article focuses on current-steering DACs, but pipeline ADCs can behave similarly.

Current-steering DACs consist of constant current sources connected to switches that steer the current to either the primary or complementary outputs, depending on the digital input value. Figure 1 shows a comparison of different sizing methods for the current sources. Current sources can be: a) equally sized (also known as thermometer encoded); or b) binary sized (N sources scaled in powers of two). However, these schemes do not extend well to high resolution. In practice, a combination of thermometer and binary encoding is used to reduce the number and size difference of current sources (Figure 1c ).

Figure 1

Comparison of different DAC architectures.

Comparison of different DAC architectures.

As the current sources do not match perfectly, a nonlinearity occurs as the digital input value changes from the sum of smaller sources to one larger source. A measure of nonlinearity is the integral nonlinearity (INL), which is defined as the deviation of the actual analog output from the ideal output. For a 16-bit DAC, the error can be larger than several least significant bits (LSBs). Figure 2 shows an INL curve with exaggerated mismatch and the resulting output signal and spectrum for a sine wave.

Figure 2a

Figure 2b

Figure 2c

DAC INL example (2a); resulting sine wave (2b); and output spectrum (2c).

DAC INL example (2a); resulting sine wave (2b); and output spectrum (2c).

Dither is a random digital signal added to the wanted digital signal to effectively randomize the location of the INL breaks. The exact characteristics of the dither signal are not critical, which provides flexibility for band-limiting the dither at a frequency where it is easily filtered at the DAC output. If the signal is at low frequency, the dither can be placed near FS/2, where FS is the sample rate. If the signal is at an intermediate frequency, the dither can be placed at low frequency. The bandwidth of the dither is not critical. Most important is dither amplitude, which needs to be higher than the largest current sources.

To demonstrate the effectiveness of dither in improving high-order harmonics, we used a DAC34H84 to generate a 210MHz tone at 1228.8MSPS. Figure 3a shows the output spectrum between zero and 400MHz without dither, with the 5th, 11th, 13th, and 17th order harmonic distortion highlighted. In Figure 3b , the same output is shown with a 20MHz-wide dither signal added at low frequency. This reduces the higher order distortion products by >5dB (HD5 is unchanged).

Figure 3a

Figure 3b

Output spectrum without dither (3a) and with dither (3b), using the DAC34H84.

Output spectrum without dither (3a) and with dither (3b), using the DAC34H84.

The composite power of the dither signal is 14dB below the tone power. At lower amplitudes, the dither is less effective (Table 1 ).

Table 1

Effect of dither amplitude on high order harmonics

Effect of dither amplitude on high order harmonics

For high-speed pipeline ADCs, an analog dither signal is added at the input and can have similar effects to improve high-order harmonics due to mismatch in the ADC pipeline stages.

Please join us next month when we will discuss how to increase a reference drive's capability for a low-impedance load.

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About the author:

— Robert Keller is the Systems and Applications Manager for TI's high-speed data converters. He has nine years of experience supporting high-speed products in wireless infrastructure communication, test and measurement, and military systems. He received a BA in physics and mathematics from Washington University, St. Louis, and a PhD in applied physics from Stanford University. He has 10 US patents in networking and sensor applications. He may be reached at: Signal Chain Basics.

4 comments on “Signal Chain Basics #74: Band-Limited Dither Improves SFDR in High-Speed DACs

  1. Michael Dunn
    February 26, 2013

    Dither is one of my favourite things. I even wrote about it: Dithering About With Intuitive Sampling 

  2. Brad Albing
    February 26, 2013

    As delightful as your posts are (no, really), can you give us just a tiny hint to entice us to follow that link and leave the always entertaining Planaet Analog site?

  3. Michael Dunn
    February 26, 2013

    I thought the title might be enticement enough!

    Well, OK. It's a very broad and intuitive look at dither – and part of a whole sampling theory series I ran. I know this isn't Planet Mixed-Signal,  but it's always good to stretch one's horizons. After all, this very blog discusses DACs…

  4. Brad Albing
    February 27, 2013

    I'll pop over to Scope Junction and check it out. And maybe steal some of the material for one of my blogs. Thanks.

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