High-speed digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) have different distortion properties than other analog components. The more purely analog components such as amplifiers are ideally linear and saturate smoothly. But DACs and ADCs can exhibit abrupt steps in their transfer functions. As a result, they don't exhibit the predictable and dominant second- and third-order harmonic distortion (HD2 and HD3).
The commonly used architectures for high-speed DACs and ADCs, such as current steering DACs and pipeline ADCs, both rely on component matching between high- and low-resolution bits in their architectures, and non-ideal matching produces abrupt steps in the input/output transfer function. This article focuses on current-steering DACs, but pipeline ADCs can behave similarly.
Current-steering DACs consist of constant current sources connected to switches that steer the current to either the primary or complementary outputs, depending on the digital input value. Figure 1 shows a comparison of different sizing methods for the current sources. Current sources can be: a) equally sized (also known as thermometer encoded); or b) binary sized (N sources scaled in powers of two). However, these schemes do not extend well to high resolution. In practice, a combination of thermometer and binary encoding is used to reduce the number and size difference of current sources (Figure 1c ).
As the current sources do not match perfectly, a nonlinearity occurs as the digital input value changes from the sum of smaller sources to one larger source. A measure of nonlinearity is the integral nonlinearity (INL), which is defined as the deviation of the actual analog output from the ideal output. For a 16-bit DAC, the error can be larger than several least significant bits (LSBs). Figure 2 shows an INL curve with exaggerated mismatch and the resulting output signal and spectrum for a sine wave.
Dither is a random digital signal added to the wanted digital signal to effectively randomize the location of the INL breaks. The exact characteristics of the dither signal are not critical, which provides flexibility for band-limiting the dither at a frequency where it is easily filtered at the DAC output. If the signal is at low frequency, the dither can be placed near FS/2, where FS is the sample rate. If the signal is at an intermediate frequency, the dither can be placed at low frequency. The bandwidth of the dither is not critical. Most important is dither amplitude, which needs to be higher than the largest current sources.
To demonstrate the effectiveness of dither in improving high-order harmonics, we used a DAC34H84 to generate a 210MHz tone at 1228.8MSPS. Figure 3a shows the output spectrum between zero and 400MHz without dither, with the 5th, 11th, 13th, and 17th order harmonic distortion highlighted. In Figure 3b , the same output is shown with a 20MHz-wide dither signal added at low frequency. This reduces the higher order distortion products by >5dB (HD5 is unchanged).
The composite power of the dither signal is 14dB below the tone power. At lower amplitudes, the dither is less effective (Table 1 ).
For high-speed pipeline ADCs, an analog dither signal is added at the input and can have similar effects to improve high-order harmonics due to mismatch in the ADC pipeline stages.
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- Download these datasheets: DAC34H84.
- For more information about data converters, visit: TI Data Converters.
About the author:
— Robert Keller is the Systems and Applications Manager for TI's high-speed data converters. He has nine years of experience supporting high-speed products in wireless infrastructure communication, test and measurement, and military systems. He received a BA in physics and mathematics from Washington University, St. Louis, and a PhD in applied physics from Stanford University. He has 10 US patents in networking and sensor applications. He may be reached at: Signal Chain Basics.